65nm下电容的失配问题

goodsilicon

因為兩邊中譯大不同
所以我大部分用英文
有些人叫這種 capacitor MOM
但是我認為 very confusing.  
在 ...
fhchen2002 发表于 2011-1-14 09:45

                               
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   OK, I see 了，case by case! thanks fhchen兄！
   

scorpio1979

very good

fhchen2002

In In the paper "Capacity Limits and Matching Properties of Integrated Capacitors"
There is an HPP capacitor, which is made of horizontal plates of metal (M_N & M_N+1) and IMD oxide.
Don't confuse this HPP capaictor with the MiM capacitor the foundry provides (for mixed-signal design).

In this papaer, it says the vertical parallel plate capacitor (VPP) has maching characteristics much better than HPP.
(Refer to the sigma_c / C_average column.)
That is it.

For those who can't get VPP matching chracterstics reports from foundry, refer to the data above (pasted from the paper).

Elaboration
You lay out a capacitor about 19 pF.  The 1-sigma variation is about 0.54%.
The mismatch between two identical such capacitor pattern would be ~= sqrt(2) * 0.54% ~= 0.764%

Compare this number with the data in the MiM characterization report.
Then we have an idea which type of capacitor has better matching characteristics.  (In the bulk part.)

Can somebody do this (i.e., make such comparison) and let us know the answer?

fuyibin

In In the paper "Capacity Limits and Matching Properties of Integrated Capacitors"
There is an HPP  ...
fhchen2002 发表于 2011-1-14 13:02

                               
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for example, we can get some information from the capacitor matching characteristic report supplied by foundry
MOM cap 98.9fF   35.6um^2      mismatch=0.042%   2.7fF/um^2
MIM cap   220fF   116.6um^2     mismatch=0.068%  1.88fF/um^2
especially for large size cap, MIM cap matching will degrade if its area is larger than some value.
I think the uniformity of the dielectric layer will be worse when area increasing.
The MOM cap is the cap between metal finger. The uniformity of dielectric layer is depended on lithography accuracy.

fhchen2002

Side-by-side layout:
The MiM data from my side looks very much like yours.
10X10: 1-sigma mismatch: 0.0789% -> 0.05x% if area doubles.

Cross-coupled layout
The MiM mismatch data from my side is better than what you provided by 50%.
2X (10X10) the mismatch (1-sigma) is only 0.0353%.

Did your "MOM" mismatch characterization report also characterize the data for (cross-coupled) common-centroid layout pattern?

semico_ljj

解釋的好。。。

vdslafe

回复 24# fuyibin

学习了，太牛了

goodsilicon

Side-by-side layout:
The MiM data from my side looks very much like yours.
10X10: 1-sigma mismatch ...
fhchen2002 发表于 2011-1-14 15:59

                               
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我也只见到过side by side的数据，看来用这个做设计还是比较保守的。一般做匹配都会cross-couple一下的。

fhchen2002

问题是 cross-coupled layout style 再搭配 scrambling
難度相當高
想像要作一個 SAR ADC
1X unit capacitor 先作 cross-coupled layout style,
另外有一 dummy 1X 和它搭配
Unit capacitor 以上為了要 improve matching 於是設法把
2X, 4X, ... 打散

yf.hu

thanks