65nm下电容的失配问题

duling653

获益匪浅啊！
我准备用这个工艺做一个SAR ADC，对电容失配的要求大概是13‰以下（采用了自校正），但是foundry那边确实还没有关于电容失配这方面的数据，请问fhchen2002兄根据你的经验，在65nm下要达到13‰以下的失配，单位电容取怎样的量级合适呢，20fF？50fF？80fF？100fF？

fhchen2002

Sorry, I do not have firm answer for you.
Without the inputs from foundries, I would take 50 fF as an aggressive design, and 80 fF as a conservative design.

Be sure you understand the mismatch statistics correctly.

Mismatch methodology:
Capacitance mismatch (\Delta C/C) = 2 * (C1 – C2)/(C1 + C2) * 100,   Unit: %

So when you say 13%, I assume you mean the standard deviation (1-sigma) of the above measurement results.  (i.e., differences of capacitance of two identical capacitor layout).

seawang

thanks！

These are the assumptions: You want to specify minimum width (of all conducting layers) to maximi ...
fhchen2002 发表于 2010-12-25 17:34

                               
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goodsilicon

这种电容和MIM比，哪一个匹配更好些？

fhchen2002

回复 13# seawang


    Sorry for more correction:

Not just the minimum width,
I should have written: "the minimum width that vias can be put along the metal lines.
Thus the upper layer metal can be shorted to lower layer metal."

fhchen2002

回复 14# goodsilicon


    當然是 MiM

主要有兩個 Key factors 來決定:
Vertical wall(s) 是否為連續平滑的 plane?
(The answer is negative,因為有 vias, and holes bewteen vias.)
而 MiM 的 top plate and bottom plate 則無此 issue

此外
MiM所使用的 dielectric 一般為 nitride
dietrice constan 為 7.5
要達到同樣的 capacitance per unit area 厚度較 oxide 為厚
因此 thickness uniformity 較佳
(corner case capacitance variation is only +/- 10%.)

而一般所用的 interl metal dielectrica 主要還是以 oxide 為主
當然在 0.13-um 以下的銅製程
會有 oxide-nitride-oxide (ONO) sandwitch 來隔絕水汽
避免 copper erosion 的情況
基本上 IMD (inter-metal dielectric) 的 dielectric material 的quality 是不能和 MiM 的 nitride 相提並論的

fuyibin

回复  goodsilicon


    當然是 MiM

主要有兩個 Key factors 來決定:
Vertical wall(s) 是否為連 ...
fhchen2002 发表于 2011-1-13 18:42

                               
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Actually, the matching characteristic of MIM cap is much worse than MOM cap

fhchen2002

回复 14# goodsilicon


Foundry data 不便 disclose   
请參考 paper
R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of
Integrated Capacitors,” JSSC March 2002, pp. 384-393.
前面楼上可以直接 download

goodsilicon

回复  goodsilicon


    當然是 MiM

主要有兩個 Key factors 來決定:
Vertical wall(s) 是否為連 ...
fhchen2002 发表于 2011-1-13 18:42

                               
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    很给面子，一路都是e文，到我这里就是国语了，呵呵，谢谢啊！
兄台的意思是MIM的匹配要好于MOM哈？
后面fuyibin兄的意思是MIM的匹配要差于MOM哈？
我该follow哪个呢？

fhchen2002

因為兩邊中譯大不同
所以我大部分用英文
有些人叫這種 capacitor MOM
但是我認為 very confusing.  
在不同的 paper 中
我也見過用 MOM 這個 terminology, 結果 device profile 是我們俗稱的 MIM.

Which has better matching property depends on foundry characterization report.
If you don't have this technical report, you can't determine the size of your unit capacitance.

In case you have 5 metal layers or more in advanced CMOS technology, you can implement area-efficient (I prefer calling it vertical parallel plate) capacitors on chip.
Using MiM capacitor will result in one extra mask layer, therefore more expensive than without.

But beware, the vertical walls are built high, and most likely from M2 to M_top.
So the signal cross-couple to the their neighbors are severe.
In order to minimize unwanted signal cross-couple, you want to keep these capacitors away from their neighbors.
From this point of view, MoM is not that area efficient.