12bit SAR ADC 0.5um Prcoess Size < 300x300

mitchell0001

Hi, All:
     12bits SAR ADC

      True is 10bits, Full Range.
       转换速率：同步clock的架构就在4 to 8 MHz.
      Calibration: NO.
      
      面临的问题是：
      Full Range, 0 to 3.3
      
      Any detail document can share it.  
      First time design. No relation Database.

Thanks
   

lvxp

with or without input rail-to-rail buffer？
with：linearity limited for gnd/vrefp；
without：sampling time and input source resistance limited；
application depends

mitchell0001

   

lvxp 发表于 2025-11-18 11:46
with or without input rail-to-rail buffer？
with：linearity limited for gnd/vrefp；
without：samplin ...

Hi,Sir:
    Without input Rail-to Rail Buffer
    The limit is the VDD to Gnd with Good INL/DNL  with Sampling phase some clocks
    The structure is Main DAC 7 bit  (Cap array) , Sub DAC 5 bit (Resistor Ladde)

Any suggestion

Thanks
   

lvxp

   

mitchell0001 发表于 2025-11-19 11:18
Hi,Sir:
    Without input Rail-to Rail Buffer
    The limit is the VDD to Gnd with Good INL/DNL  w ...

why choose 12bits distributed to cap and res separately？

mitchell0001

Reference the origin design (10bits) to extension to 12bits.
But the origin Database is not good.  So it need to enhance to 12bits for Products application.