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发表于 2024-12-31 19:43:39
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参看文献【1】的Fig.10。CMOS工艺通常用的轻掺杂硅衬底电阻率在10Ωcm左右(这是带有Native层的衬底的电阻率)。如果不带有Native层,则电阻率会在0.1-1Ωcm左右。
【1】S. Hazenboom, T. S. Fiez and K. Mayaram, "A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs," in IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 574-587, March 2006, doi: 10.1109/JSSC.2006.869790. |
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