Verdi 遇到 undefined module 问题

jumpyoung · 发表于 2024-11-22 18:37:31

求助：使用VCS仿真Xilinx IP,按照网上的步骤编译Vivado的 VCS仿真库，没有报错。
使用Makefile脚本compile、elaborate、sim都没有error和warning.
但是用Verdi打开设计时，Xilinx的 IP 都是 undefined mudule.谁知道这个怎么解决吗？
报错截图

手动添加编译Vivado安装目录下的data/src文件太麻烦。VCS和Vivado版本也是兼容的。

A1985 · 发表于 2024-11-24 10:05:57

本帖最后由 A1985 于 2024-11-24 10:07 编辑

需要编译xilinx自带的模型库，都在安装vivado目录里面，或者用compilesimlib或者gui的compile sim lib vcs

kk316 · 发表于 2024-11-24 10:50:41

makefile 脚本怎么写的，看看？setup 文件呢

jumpyoung · 发表于 2024-11-24 12:09:50

本帖最后由 jumpyoung 于 2024-11-24 16:29 编辑

kk316 发表于 2024-11-24 10:50
makefile 脚本怎么写的，看看？setup 文件呢

f_v = ./Temp/filelist_v.f
f_sv = ./Temp/filelist_sv.f
verdi_dir = /usr/Synopsys/verdi/R-2020.12-SP1/share/PLI/VCS/linux64
glbl_home = /usr/Xilinx/Vivado2022.1/Vivado/2022.1/data/verilog/src
SIM_PATH =$(shell pwd)
SRC_PATH =$(SIM_PATH)/Source
macro_sim =$(SIM_PATH)/Macro
Bench_Home =$(SIM_PATH)/Testbench
Bench_File =$(notdir $(wildcard $(Bench_Home)/*.v $(Bench_Home)/*.sv))
Bench_Name =$(basename $(Bench_File))
all: clean filelist compile elaborate simulate verdi
compile:
vlogan \
-full64 \
-work Xilinx_Lib \
$(SIM_PATH)/Temp/glbl.v \
-f $(f_sv) \
-f $(f_v) \
+v2k \
-override_timescale=1ps/1ps \
+warn=all \
+incdir+$(macro_sim) \
-l $(SIM_PATH)/Temp/VCS/Compile.log \
-sverilog \
+define+SIMULATION_EN
elaborate:
vcs \
-full64 \
-Mdir=$(SIM_PATH)/Temp/VCS/work \
-sverilog \
-override_timescale=1ps/1ps \
-lca \
+lint=TFIPC-L \
+lint=PCWM \
-debug_acc+all \
-P $(verdi_dir)/novas.tab $(verdi_dir)/pli.a \
-cm line+cond+fsm+tgl+branch \
-cm_dir $(SIM_PATH)/Temp/VCS/ \
-cm_log Coverage.log \
-l $(SIM_PATH)/Temp/VCS/Elaborate.log \
Xilinx_Lib.glbl \
Xilinx_Lib.$(Bench_Name) \
-o $(SIM_PATH)/Temp/VCS/simv
simulate:
$(SIM_PATH)/Temp/VCS/simv -l $(SIM_PATH)/Temp/VCS/Simulate.log +notimingcheck +nospecify -k $(SIM_PATH)/Temp/VCS/ucli.key
verdi:
verdi -sv -f $(f_sv) -f $(f_v) -top $(Bench_Name) -ssf $(SIM_PATH)/WaveFile/*.fsdb
clean:
@rm -rf csrc DVEfiles simv simv.daidir ucli.key VCS* AN.DB 64 verdiLog
@rm -rf novas.*
@rm -rf *.log *.vpd *.ddc *.svf *.SDF *Synth *Netlist* work vsim* transcript
@rm -rf ./Temp
@mkdir ./Temp
@mkdir ./Temp/VCS
@mkdir ./Temp/VCS/work
filelist:
@cp $(glbl_home)/glbl.v $(SIM_PATH)/Temp
[url=home.php?mod=space&uid=205858]@find[/url] $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.v" >Temp/filelist_v.f
@find $(SIM_PATH)/Macro/ -name "*.h" >Temp/filelist_h.f
@find $(SIM_PATH)/Testbench/ -name "*.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Model/ -name "*.v" >>Temp/filelist_v.f
@find $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.sv" >Temp/filelist_sv.f
@find $(SIM_PATH)/Testbench/ -name "*.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Model/ -name "*.sv" >>Temp/filelist_sv.f
help:
@echo[/url] "******Welcome******"
@echo " COMMAND LIST: "
@echo "1--- make clean "
@echo "2--- make filelist "
@echo "3--- make compile "
@echo "4--- make elaborate "
@echo "5--- make simulate "
@echo "6--- make verdi "
@echo "7--- one-click simulation, please use the command --- make all"

复制代码

使用 Vivado编译好的仿真库放在/usr/Xilinx/VivadoLib/目录下了
synopsys_sim.setup

Xilinx_Lib : ./Temp/VCS/work
OTHERS=/usr/Xilinx/VivadoLib/synopsys_sim.setup

复制代码

jumpyoung · 发表于 2024-11-24 12:17:42

kk316 发表于 2024-11-24 10:50
makefile 脚本怎么写的，看看？setup 文件呢

您好，感谢回复我的帖子，makefile是我在知乎上找的，稍微改了改，可以跑起来

f_v = ./Temp/filelist_v.f
f_sv = ./Temp/filelist_sv.f
verdi_dir = /usr/Synopsys/verdi/R-2020.12-SP1/share/PLI/VCS/linux64
glbl_home = /usr/Xilinx/Vivado2022.1/Vivado/2022.1/data/verilog/src
SIM_PATH =$(shell pwd)
SRC_PATH =$(SIM_PATH)/Source
macro_sim =$(SIM_PATH)/Macro
Bench_Home =$(SIM_PATH)/Testbench
Bench_File =$(notdir $(wildcard $(Bench_Home)/*.v $(Bench_Home)/*.sv))
Bench_Name =$(basename $(Bench_File))
all: clean filelist compile elaborate simulate verdi
compile:
vlogan \
-full64 \
-work Xilinx_Lib \
$(SIM_PATH)/Temp/glbl.v \
-f $(f_sv) \
-f $(f_v) \
+v2k \
-override_timescale=1ps/1ps \
+warn=all \
+incdir+$(macro_sim) \
-l $(SIM_PATH)/Temp/VCS/Compile.log \
-sverilog \
+define+SIMULATION_EN
elaborate:
vcs \
-full64 \
-Mdir=$(SIM_PATH)/Temp/VCS/work \
-sverilog \
-override_timescale=1ps/1ps \
-lca \
+lint=TFIPC-L \
+lint=PCWM \
-debug_acc+all \
-P $(verdi_dir)/novas.tab $(verdi_dir)/pli.a \
-cm line+cond+fsm+tgl+branch \
-cm_dir $(SIM_PATH)/Temp/VCS/ \
-cm_log Coverage.log \
-l $(SIM_PATH)/Temp/VCS/Elaborate.log \
Xilinx_Lib.glbl \
Xilinx_Lib.$(Bench_Name) \
-o $(SIM_PATH)/Temp/VCS/simv
simulate:
$(SIM_PATH)/Temp/VCS/simv -l $(SIM_PATH)/Temp/VCS/Simulate.log +notimingcheck +nospecify -k $(SIM_PATH)/Temp/VCS/ucli.key
verdi:
verdi -sv -f $(f_sv) -f $(f_v) -top $(Bench_Name) -ssf $(SIM_PATH)/WaveFile/*.fsdb
clean:
@rm -rf csrc DVEfiles simv simv.daidir ucli.key VCS* AN.DB 64 verdiLog
@rm -rf novas.*
@rm -rf *.log *.vpd *.ddc *.svf *.SDF *Synth *Netlist* work vsim* transcript
@rm -rf ./Temp
@mkdir ./Temp
@mkdir ./Temp/VCS
@mkdir ./Temp/VCS/work
filelist:
@cp $(glbl_home)/glbl.v $(SIM_PATH)/Temp
[url=home.php?mod=space&uid=205858]@find[/url] $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.v" >Temp/filelist_v.f
[url=home.php?mod=space&uid=205858]@find[/url] $(SIM_PATH)/Macro/ -name "*.h" >Temp/filelist_h.f
[url=home.php?mod=space&uid=205858]@find[/url] $(SIM_PATH)/Testbench/ -name "*.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.v" >>Temp/filelist_v.f
@find $(SIM_PATH)/Model/ -name "*.v" >>Temp/filelist_v.f
@find $(SRC_PATH) -path "$(SRC_PATH)/Ipcore" -prune -o -type f -name "*.sv" >Temp/filelist_sv.f
@find $(SIM_PATH)/Testbench/ -name "*.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Ipcore/ -name "*netlist.sv" >>Temp/filelist_sv.f
@find $(SIM_PATH)/Model/ -name "*.sv" >>Temp/filelist_sv.f
help:
[url=home.php?mod=space&uid=17569]@echo[/url] "******Welcome******"
@echo " COMMAND LIST: "
@echo "1--- make clean "
@echo "2--- make filelist "
@echo "3--- make compile "
@echo "4--- make elaborate "
@echo "5--- make simulate "
@echo "6--- make verdi "
@echo "7--- one-click simulation, please use the command --- make all"

复制代码

setup文件如下

Xilinx_Lib : ./Temp/VCS/work
OTHERS=/usr/Xilinx/VivadoLib/synopsys_sim.setup

复制代码

jumpyoung · 发表于 2024-11-24 16:22:18

A1985 发表于 2024-11-24 10:05
需要编译xilinx自带的模型库，都在安装vivado目录里面，或者用compilesimlib或者gui的compile sim lib vcs ...

您好，仿真库我已经编译好了，VCS仿真也没告警，问题出在Verdi好像识别不出来这些编译好的库

ALLINFORU · 发表于 2024-11-25 15:59:49

可以试试在vcs选项加入-kdb，然后在verdi选项加入-dbdir $(SIM_PATH)/Temp/VCS/work/simv.daidir

jumpyoung · 发表于 2024-11-26 14:17:53

ALLINFORU 发表于 2024-11-25 15:59
可以试试在vcs选项加入-kdb，然后在verdi选项加入-dbdir $(SIM_PATH)/Temp/VCS/work/simv.daidir ...

您好，我在makefile的 elaborate时加入了 -kdb选项，然后 elaborate就报错了
Makefile:
捕获1.PNG

报错log:显示 XILINX_LIB 库和UNISIM_VER这两个库 kdb选项不一致
捕获.PNG

附：
这是我使用 Vivado 下预编译VCS仿真库的tcl命令

compile_simlib -simulator vcs -simulator_exec_path {/home/kkk/Synopsys/vcs/V-2023.12-SP2/bin} -family all -language all -library all -dir {/home/kkk/WorkSpace/Vivado2022_VCS2023_SimLib} -no_systemc_compile

复制代码

jumpyoung · 发表于 2024-11-30 10:40:46

求教，悬而未决

jumpyoung · 发表于 2024-12-2 12:29:32

求助

[求助] Verdi 遇到 undefined module 问题

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