Logic Synthesis and Verification Algorithms

intermilan

1996版的，找不到2006新版的电子版本
不过好像改动不多

1 of 7

intermilan

2 of 7

intermilan

3 of 7

intermilan

4 of 7

intermilan

5 of 7

intermilan

6 of 7

intermilan

7 of 7

intermilan

Editorial Reviews
Book Description
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

intermilan

Table of Content

loveineda

楼主变态!!!!!火星人刚发过就来转发,什么意思哦,这里是你来做生意的地方吗!!!!??????