VCS在sim时对异步复位同步释放的寄存器报hold的violation问题，谢谢

IC牛马

求助各位前辈，我的设计中由于时钟域很多，复位方式为异步复位同步释放，使用两级寄存器打拍，以其中一个为例，每个都一样，代码为


always @(posedge Clk_VF1 or negedge RstN_I) begin
   if(!RstN_I) begin
       RstN_S1        <= 1'b0;
       RstN_VF1 <= 1'b0;
   end else begin
       RstN_S1        <= 1'b1;
       RstN_VF1        <= RstN_S1;
   end
end

把VF1作为Clk_VF1时钟域下的复位端，我处理的思路是在DC阶段对二级寄存器的QN端进行set dont touch和set ideal network，如下：
set_dont_touch_network [get_pins T1/G1/D3/RstN_VF1_reg/QN] ;
set_ideal_network [get_pins T1/G1/D3/RstN_VF1_reg/QN] ;

然后在ICC2013后端place之前，解除ideal_network属性，以让后端按fanout去处理同步释放后的rst，指令如下
remove_ideal_network [get_pins T1_G1_D3_RstN_VF1_reg/QN] ;
最后做pt的时候也没有时序违例，也没有rec/rom的报错（进行了检查），另外对[get_pins T1/G1/D3/RstN_VF1_reg/QN] 也尝试过在DC中设置false path等，对结果也没影响，但是在vcs的sim阶段对异步复位同步释放的寄存器报了violation，如下：

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF1_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S1_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF2_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S2_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_SYNC_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 76 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_S1_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 487 );


"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF1_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S1_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF2_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S2_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 474 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_SYNC_REG
    $hold( posedge CK:1205000000, posedge SN:1205000000, limit: 76 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D4.RSTN_S1_REG
    $hold( posedge CK:1205000000, posedge RN:1205000000, limit: 487 );

请问各位前辈这是我对异步复位同步释放的前后端处理方式不对么，还是由什么其它原因造成的，如果有不合适的地方应该如何修改我上面的指令。因为仿真跑出的结果某个信号在经历一次组合逻辑变化后变为不定态，由于服务器vcs软件环境问题原因无法使用show schematic等操作分析根源，所以怀疑是上面的原因导致，并且上面的警告也不让我放心，请教下前辈们，谢谢

jake

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/verilog/DBH_1533IL11SJ_GE1P5V.v", 2954: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_VF1_REG
    $hold( posedge CK:100000000, posedge SN:100000000, limit: 64 );

"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/VERILOG/DBH_1533IL11SJ_GE1P5V.v", 2782: Timing violation in tb_Time_Top.Time_Top_inst.T1_G1_D3_RSTN_S1_REG
    $hold( posedge CK:100000000, posedge RN:100000000, limit: 474 );


这里报的hold violation应该就是removal violation，建议打开标准元的Verilog文件看一下。
有的标准元库Verilog文件使用合并的$recrem，有的使用分开的$removal, $recovery，有的使用$setuphold或分开的$setup, $hold，通常Verilog model会有`ifdef RECREM，让用户选择那一种方式。

这里有另一个问题，复位同步有些DFF用的是RN复位类型的，有些是SN置位类型的，需要检查一下，看一下电路。通常复位同步电路不希望工具综合，而是直接在RTL里例化。

jake

供参考：
https://blog.eetop.cn/blog-1592-6946122.html

IC牛马

jake 发表于 2024-8-20 21:49
"/disk2/D23_wangyunfeng/Syn_Lib/DBH_STD_1533IL11SJ_GE1P5V_21Q2_V3.4.10/verilog/DBH_1533IL11SJ_GE1P5V ...

谢谢您的回复，我的复位电路如果例化为一个单独的模块再调用的话，综合工具也会综合，和直接写出来的是一样的，请教下您，您的意思是复位电路不让DC综合的话，是自己写具体类型的FF然后set dont touch么，这样的目的是什么。另外我看了下库的verilog，只有recovery，没有removal，也没有ifdef，如图，这种情况应该怎么办，sta是已经过了的，谢谢前辈！另外您说的最后一个问题确实是，两级同步寄存器一个被综合为SN的，一个被综合为RN的，这样有什么影响么，谢谢前辈！！！

jake

IC牛马 发表于 2024-8-20 08:23
谢谢您的回复，我的复位电路如果例化为一个单独的模块再调用的话，综合工具也会综合，和直接写出来的是一 ...

                               
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这里确实用了$hold代替$removal，理论上是可以的。
如果功能没问题的话，这几个DFF的removal, recovery不报就可以了。
方法1: 改sdf，把这几个DFF的removal, recovery改成0。
方法2: 查VCS手册，命令行设置，让VCS不查这几个DFF的removal，recovery。抱歉，我不用VCS。

IC牛马

jake 发表于 2024-8-20 22:33
这里确实用了$hold代替$removal，理论上是可以的。
如果功能没问题的话，这几个DFF的removal, recovery ...

好的，谢谢前辈，确实不是影响后仿结果的原因，另外我觉得也和tb的复位释放有关，在修改外部rstn的释放时间后，使其不与各异步时钟的上升沿恰好理想对其，该vio会无。