PLL Jitter, PhaseNoise cadence 仿真

jamesccp

非常棒！！

im2058

david_reg 发表于 2024-4-4 18:27
Thanks for the detail sharing.
I am just studying the PLL simulation these days. Here are another ...

Thanks for the detail sharing.
I am just studying the PLL simulation these days. Here are another two comments for discussion:

1. in P19, the spectre noise analysis result of LPF will only give one-sided PSD Sn(f), when it is used in PLL phase domain model simulation for phase noise estimation, I think two-sided PSD i.e. Sn(f)/2 should be used.
Comments: Actually, I'm not very sure that the noise type spectre gives is SSB or DSB. I try to find it in Cadence help doc, but failed to find it(if possible, can you tell where you see it).  So I just use the raw data. (Another one is that Sn(f)/2 or Sn(f)*2, typo here??).


2. in P38, the "Direct plot form" function of sampled pnoise

    "Output Noise": I think this is the DSB noise voltage PSD Sv(f) (V^2/Hz) at the cross point;
    "Edge Phase Noise" I think this is the SSB phase noise PSD Sp(f) (dBc/Hz) at the cross point;
    their relationship is
     Sp(f) (dBc/Hz) = 10*log10(Sv(f)/2*(2*pi*f0/SR)^2)
   where f0 is the PSS fund, SR is the slew rate at the cross point.

Comments: If possible, can you tell where you see this equation? I can try to use your equation to do a correlation later.

binnq

感谢

david_reg

im2058 发表于 2024-4-7 18:54
Thanks for the detail sharing.
I am just studying the PLL simulation these days. Here are another  ...

for the relatioin between Edge phase noise and sampled output noise, you can refer to this link. I also have verified it in one of my simulation, you can also try to do a numerical verification.
https://community.cadence.com/ca ... d-pnoise-simulation

david_reg

im2058 发表于 2024-4-7 18:54
Thanks for the detail sharing.
I am just studying the PLL simulation these days. Here are another  ...

about the 1st point, I didn't find any document about the noise analysis output. I just did an estimation with a simulation. for example, you can simulate a resistor output  noise with Spectre noise analysis, you could find out that the results PSD is about 4KTR. So I think this analysis will only give out "one-sided" PSD.

while in this book

B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level, 1st ed. Cambridge University Press, 2020.

An example to calculate the phase noise of VCO is given as below. It use "two-sided" PSD before VCO phase model. So I think the loop filter noise analysis result PSD should be divided by 2 in the phase model simulation.

                               
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jiaoda

Good Job，讲PLL理论很多，但是专门讲PLL模块仿真资料其实很少，希望能继续更新。

hamandu

学习，谢谢分享

accel30

DINGDING

LeiHu

thanks

a104842708

楼主有电路example吗？