ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling

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ASIC AND FPGA VERIFICATION:A GUIDE TO COMPONENT MODELING

RICHARD MUNDEN


The Morgan Kaufmann Series in Systems on Silicon
Series Editors: Peter Ashenden, Ashenden Designs Pty. Ltd. and Adelaide University, and
Wayne Wolf, Princeton University
The rapid growth of silicon technology and the demands of applications are
increasingly forcing electronics designers to take a systems-oriented approach to
design. This has led to new challenges in design methodology, design automation,
manufacture and test. The main challenges are to enhance designer productivity
and to achieve correctness on the first pass. The Morgan Kaufmann Series in
Systems on Silicon presents high quality, peer-reviewed books authored by leading
experts in the field who are uniquely qualified to address these issues.
The Designer’s Guide to VHDL, Second Edition
Peter J. Ashenden
The System Designer’s Guide to VHDL-AMS
Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden
Readings in Hardware/Software Co-Design
Edited by Giovanni De Micheli, Rolf Ernst, and Wayne Wolf
Modeling Embedded Systems and SoCs
Axel Jantsch
Multiprocessor Systems-on-Chips
Edited by Wayne Wolf and Ahmed Jerraya
Forthcoming Titles
Rosetta User’s Guide: Model-Based Systems Design
Perry Alexander, Peter J. Ashenden, and David L. Barton
Rosetta Developer’s Guide: Semantics for Systems Design
Perry Alexander, Peter J. Ashenden, and David L. Barton
Functional Verification
Bruce Wile, John Goss, and Wolfgang Roesner
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Project Manager Brandy Palacios Copyeditor Graphic World
Project Management Graphic World Proofreader Graphic World
Developmental Editor Nate McFadden Indexer Graphic World
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Cover Design Chen Design Associates Cover printer Phoenix Color
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Reprinted with permission from IEEE Std. 1076.4-2000, Copyright 2000 by IEEE, “IEEE
Standard VHDL Language Reference Manual”; IEEE Std. 1076.4-1995, Copyright 1995 by
IEEE, “Structure of a VITAL Model”; and IEEE Std.1497-2001, Copyright 2001 by IEEE, “IEEE
Standard for Standard Delay Format (SDF) for the Electronic Design Process.” The IEEE disclaims
any responsibility or liability resulting from the placement and use in the described
manner.
Library of Congress Cataloging-in-Publication Data: Application Submitted
ISBN: 0-12-510581-9
Printed in the United States of America
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i_test

ASIC and FPGA Verification - A Guide to Component Modeling

nieyang888

:victory:

loveineda

是不是把"幽灵"大侠的书转发拉!!
贱!!!!

ewb1

下来看看，谢谢分享

0xffff

好书
谢谢l

lixqing

谢谢l

eetime999

TKS!!!!!!!!!!!!!!!!!

i_test

“是不是把"幽灵"大侠的书转发拉”

应该没有。我在BBS上没有搜到这本书。

gge_007

我一定要下载