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发表于 2024-1-24 10:55:06
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本帖最后由 gratwo 于 2024-1-24 13:40 编辑
大工艺节点的不均匀性严重
40nm开始不均匀性不明显了
小节点(40nm)工艺考虑trigger vol和 hold vol之间的窗口
大节点(>=90)考虑uniformity
With the process advancing from 90nm to 40nm,
GGNMOS ESD robustness decreases sharply, while trigger
voltage and holding voltage increases. So, same structure
GGNMOS implemented in 90nm as an excellent ESD
protection, will be not fit to 40nm process.
同一个工艺下,大节点,L的增加It2迅速下降
40nm,随L增加,It2下降不明显。the thin oxide
thickness becomes the constraint under 40nm process, and L is
no longer the main factor to affect the failure current.
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