运算放大电路设计

Nagisama123

zju蜗牛 发表于 2023-6-16 11:15
我用的是0.9v电压源，感觉偏置不太好做啊

噢，0.9v电压源的话很难做gain boosting，swing不够的。GBW要到1G的话，电流应该要求比较大吧。这种我觉得用两级或者folded可能会好一点。

icdane

zju蜗牛 发表于 2023-6-16 11:12
帖子没说清楚，0.9V电压源，单位增益带宽要达到1G，用一级的话，我是折叠共源共栅，感觉偏置比较难做
...

use two stage, give the first stage x100, second stage x10y, and bandwidth 1g is achievable

icdane

icdane 发表于 2023-6-16 11:51
use two stage, give the first stage x100, second stage x10y, and bandwidth 1g is achievable

you may consider only core devices

zju蜗牛

icdane 发表于 2023-6-16 11:51
use two stage, give the first stage x100, second stage x10y, and bandwidth 1g is achievable

thanks a lot, I'll try it

zju蜗牛

icdane 发表于 2023-6-16 11:53
you may consider only core devices

for the vdd is so limited(0.9V), it's very hard to bias the OTA though I use the gm/Id method,(when I change the vdd to 1.2V, it's fine),so could you give me any advice on biasing this circuit?

                               
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Lilyya

LZ你好，我也是基于28nm工艺做同样规格的运放，能给一些指导吗？