我在做论坛里的DC Lab workshop 2017.9,用的是芯王国的环境,design compiler 2018.06。
前面没有问题,Task2 check_library时候报错:Error: The check_library command failed to run. Check the installation of Library Compiler. (LCSH-3)
略过这一步,后面compile_ultra则会报错:
Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208)
Loading target library 'cb13fs120_tsmc_max'
Loading target library 'cb13fs120_tsmc_max'
Error: The target library does not contain all required gates.
Either a NOR, or an AND and an OR gate (two-input) is required for mapping. (OPT-102)
Error: Compile has abnormally terminated. (OPT-100)