本帖最后由 轩辕志瑜 于 2023-3-17 03:24 编辑
您好,这是必应。根据我的搜索结果123,我找到了一些用verilog读写csv文件的示例代码,您可以参考一下:
这是一个用verilog读取csv文件中的正弦和余弦数据,并将其转换为二进制数的代码1:
- module sin_cos_lut(
- input clk,
- input rst,
- input [10:0] angle,
- output reg signed [17:0] sin_out,
- output reg signed [17:0] cos_out
- );
- reg signed [17:0] sin_lut[0:2047];
- reg signed [17:0] cos_lut[0:2047];
- integer file_id;
- integer i;
- integer status;
- initial begin
- file_id = $fopen("sincos.csv", "r");
- if (file_id == 0) begin
- $display("Error opening file");
- $finish;
- end
- for (i = 0; i < 2048; i = i + 1) begin
- status = $fscanf(file_id, "%d,%d\n", sin_lut[i], cos_lut[i]);
- if (status == -1) begin
- $display("Error reading file");
- $finish;
- end
- end
- end
- always @(posedge clk) begin
- if (rst) begin
- sin_out <= 18'd0;
- cos_out <= 18'd0;
- end else begin
- sin_out <= sin_lut[angle];
- cos_out <= cos_lut[angle];
- end
- end
- endmodule
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这是一个用verilog写入csv文件中的计数器值的代码2:
- module counter # (
- parameter BITS = 8;
- ) (
- input wire clock,
- input wire reset,
- output reg [BITS-1 : 0] count
- );
- integer file_id;
- initial begin
- file_id = $fopen("counter.csv", "w");
- if (file_id == 0) begin
- $display("Error opening file");
- $finish;
- end
- end
- always @(posedge clock) begin
- if (reset) begin
- count <= {BITS{1'b0}};
- end else begin
- count <= count + {BITS{1'b1}};
- // write the counter value to the csv file with a newline character at the end
- $fputc(file_id, "%d\n", count);
- end
- end
- endmodule
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