Designing Digital Systems With SystemVerilog (v2.1) @2021

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This textbook is targeted to a first college course in digital systems design. Its goal is to present the basics of combi- national and sequential logic design to enable you to create significant and complex digital systems by its conclusion. Additionally, it teaches the SystemVerilog language along with the digital design. This has the advantage that all the SystemVerilog is motivated by actual designs in the text. Thus, even if you already have a digital design background, this coupling of design and SystemVerilog will provide, I believe, an excellent platform for learning SystemVerilog (or Verilog) from scratch.

When deciding what to include and not to include in this text, I have tried to avoid content bloat — nobody really wants a 450-page text (and nobody can cover such a text in one semester). I have used my lecture notes and lecture schedule as a guide — if I spend time in class lecturing on a topic, then I considered including it in this text. If I couldn’t fit it into my course schedule, I left it out.

This book has short chapters. Each chapter introduces a topic to be covered in a lecture or, at most, two. The short chapters closely follow the organization of the course lecture slides we use. The hope is that this close match between textbook and course content will help you learn the material more easily. And, based on experience in my introductory classes, some material from previous editions has been moved to “Optional Material” sections. This is material that, while valuable to learn as you learn to design well, can be covered at any time during the course (or omitted, depending on time available).

Revision History

This version (version 2.1) contains a number of changes to the previous version beyond correcting typos or other errors. It includes expanded discussions on a variety of topics to clarify points of common student confusion observed in my courses over the past 15+ years. These include topics on flip flop timing, hierarchical SystemVerilog design, and SystemVerilog coding styles for generating outputs from counters and finite state machines. Also, additional examples were added in various places. Finally, in the SystemVerilog chapters schematics corresponding to the code samples have been added.

Brent Nelson

Department of Electrical and Computer Engineering Brigham Young University Provo, Utah March 2021 (Version 2.1)

Designing Digital Systems With SystemVerilog (v2.1) (Brent E. Nelson).pdf (5.69 MB , 下载次数: 406 )

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