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发表于 2022-8-8 13:59:47
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module mid_data(
input clk ,rst_n,
input [7:0] a,b,c,
output reg [7:0] mid_data
);
wire A,B,C;
wire [2:0] state;
assign A=(a>b)?1:0;
assign B=(b>c)?1:0;
assign C=(c>a)?1:0;
assign state={A,B,C};
always@(posedge clk)
if(!rst_n)
begin
mid_data<=8'b0;
end
else case(state)
3'd2,3'd5: begin mid_data<=a; end
3'd1,3'd6: begin mid_data<=b; end
3'd0,3'd3,3'd4: begin mid_data<=c; end
default: begin mid_data<=mid_data; end
endcase
endmodule
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任务.txt
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