12bit的SAR ADC一般可以做到多少速率？

peterlin2010

   

castrader 发表于 2022-4-25 10:04
160M 12b这个一般是通讯意义上的SARADC，在量程、增益等方面与普通的1M左右的SAR ADC定义不太一致。
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A 40-nm CMOS 12b 120-MS/s Nonbinary. SAR  


200M  pipelined-SAR ADC

40nm CMOS 12b 200MS/s Single-amplifier Dual ...


A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

https://bbs.eetop.cn/thread-614241-1-1.html

sunjimmy

2021_An 18.39 fJ-Conversion-Step 1-MSPS 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

sunjimmy

2014_An analog front end with a 12-bit 3.2-MS_s SAR ADC for a power line communication system

sunjimmy

2017_A 12-14 bit 4-2MSPS SAR ADC in 65nm Using Novel Residue Boosting_CICC17

sunjimmy

Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor-capacitor array DAC technique for wireless application

Published in: 2015 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

Abstract:
A 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. To reduce DAC switching energy and chip area, a hybrid resistor-capacitor DAC is applied. To save energy, asynchronous control logic to drive the ADC is used. A pre-amplifier based comparator circuit is built to reduce the kickback noise from the dynamic latch designs. With 1.8 V supply voltage and 5.0 MHz sampling rate, measured results achieve -0.55/0.72 LSB (Least Significant Bit) of DNL (differential nonlinearity) and -0.78/0.92 LSB of integral nonlinearity (INL) respectively, and 10.76 bits of an effective number of bits (ENOB) at 1MHz input frequency. The chip area is 0.83 mm 2 including pads and the power consumption is 490μW for optical and wireless communications.

sunjimmy

12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications

Published in: 2021 Twelfth International Conference on Ubiquitous and Future Networks (ICUFN)

Abstract:
This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for a Bluetooth Low Energy (BLE) application. The objective of this work is to reduce the number of capacitors in the Capacitor Digital to Analog Converter (CDAC). To achieve this, a hybrid type DAC has been applied where 8 Most Significant Bits (MSB)s are decided through capacitive DAC and 4 Least Significant Bits (LSB)s are decided in a Resistor DAC (RDAC). The conversion speed for this design reaches up to 6 MS/s. The prototype ADC is designed in a 90 nm complementary metal-oxide semiconductor (CMOS) process. The analog and digital supply voltage range for this design are 2.7-5.5 V and 1.1-1.3 V respectively. For 6 MS/s conversion rate, this ADC achieves up to 11.8 and 11.2 effective number of bits (ENOBs), for maximum and minimum supply voltages respectively. The current consumption from a 5 V supply voltage is 980 µA and the Figure of Merit (FOM) is 229 fJ/Conv.step.

sunjimmy

2021_12-Bit 5 MS/s SAR ADC with Hybrid Type DAC for BLE Applications

sunjimmy

A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS

Published on Apr 1, 2018 in International Journal of Circuit Theory and Applications

Summary
This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious-free dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-to-noise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step.

maverick28229

thanks for sharing infor.

骷髅书生

mark~