vcs后仿时编译报出的warnning有没有相关的官方说明文档可以查呢

瘦瘦的胖胖

类似这的一些警告，主要想知道对我的设计有没有影响

瘦瘦的胖胖

自己顶自己

jake

Description
Resolving "[SDFCOM_SWC] Simple Wire Connection" Warning
Question:

What are the reasons for VCS to generate the "SDFCOM_SWC" warning message, as
shown below?

-------------------------------------------------------------------------------
Warning-[SDFCOM_SWC] Simple Wire Connection
test.sdf, 20
module: child1, "instance: top.father.B"
  SDF Warning: The path from B.X to C.A doesn't have a simple wire connection,
  delay will still be annotated.
-------------------------------------------------------------------------------
Answer:

A simple wire connection is like connecting the same wire to the two nodes.
So in the code, even the name of the wire should not change (bit select / part
select is allowed).

If an interconnect delay is specified from point A to point B, but points A and
B are not connected by a simple wire connection (no connection at all or
connected though gates, buffers, or instances of other modules), this warning
message is generated. VCS still annotates the delay to the output port properly.

In the following example, consider that the interconnect delay is annotated
from x/a to y/b as:
-------------------------------------------------
        (CELL
          (CELLTYPE "top")
          (INSTANCE)
          (DELAY
            (ABSOLUTE
            (INTERCONNECT x/a y/b (1:2:3)(4:5:6))
            )
          )
        )
-------------------------------------------------

and the hierarchy is as shown below:
----------------------------------------------------------------------------
        // Dummy code:
        //
        module top ();
        wire a , b;
            X x (a) ;

         // Y y (a) ; // Uncommenting this line will not give any warning

            Y y (b) ; // Uncommenting this line will give SDFCOM_SWC warning
                      // because there is no simple wire connection between
                      // a and b
----------------------------------------------------------------------------


Question:
What should you do to resolve the "SDFCOM_SWC" warning?
Answer:

As this is just a notification message, you can safely ignore it.
Using the "+warn=noSDFCOM_SWC" switch at compile-time will supress this warning.

However, if the RTL is modified to establish a wire connection between "a" and
"b", using simple assignment statement, as shown below, along with b connected
to the instance "y" of module "Y", then the SDFCOM_SWC warning will not appear
and now you will run into the SDFCOM_IWSBA warning:

        assign b = a ;

-------------------------------------------------------------------------------
Warning-[SDFCOM_IWSBA] INTERCONNECT will still be annotated
test.sdf, 19
module: X, "instance: top.x"
  SDF Warning: INTERCONNECT from x.a to y.b has Continuous Assignment at
  test.v:46, delay will still be annotated.
----------------------------------------------------------------------------

zhangna19960121

同问

easonjake333

为啥我昨天的回复没审核通过