IC & System Design 2003 - Power&Timing Modeling,Optimization....

alexpanait

great to be here.

mscyc0909

Take a look! 1/3#

mscyc0909

Oh! It's a version in year 2003.
There had been a 2007 version.

mscyc0909

Take a look! 2/3#

mscyc0909

Keynote Speech
Architectural Challenges for the Next Decade Integrated Platforms . . . . . . 1
A. Cuomo (STMicroelectronics, Agrate Brianza, Italy)
Gate-Level Modeling and Design
Analysis of High-Speed Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
G. Privitera, F. Pessolano (Philips Research, Eindhoven,
The Netherlands)
Low-Voltage, Double-Edge-Triggered Flip Flop . . . . . . . . . . . . . . . . . . . . . . . 11
P. Varma, A. Chakraborty (Indian Institute of Technology, New Delhi,
India)
A Genetic Bus Encoding Technique for Power Optimization of
Embedded Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
G. Ascia, V. Catania, M. Palesi (Universit`a di Catania, Italy)
State Encoding for Low-Power FSMs in FPGA . . . . . . . . . . . . . . . . . . . . . . . 31
L. Mengibar, L. Entrena, M.G. Lorenz, R. S´anchez-Reillo (Universidad
Carlos III, Madrid, Spain)
Low Level Modeling and Characterization
Reduced Leverage of Dual Supply Voltages in Ultra Deep
Submicron Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
T. Schoenauer, J. Berthold, C. Heer (Infineon Technologies, M¨unchen,
Germany)
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic
CMOS Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
J.L. Rossell´o, J. Segura (University of Balearic Islands, Spain)
CMOS Gate Sizing under Delay Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A. Verle, X. Michel, P. Maurine, N. Az´emard, D. Auvergne (LIRMM,
Universit`e de Montpellier II, Montpellier, France)
Process Characterization for Low VTH and Low Power Design. . . . . . . . . . 70
Power and Energy Consumption of CMOS Circuits: Measurement Methods
and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
J. Rius, A. Peidro, S. Manich, R. Rodriguez (Departament d’Enginyeria
Electronica, UPC, Barcelona, Spain)
Interconnect Modeling and Optimization
Effects of Temperature in Deep-Submicron Global
Interconnect Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
M.R. Casu, M. Graziano, G. Piccinini, G. Masera, M. Zamboni
(Politecnico di Torino, Italy)
Interconnect Parasitic Extraction Tool for Radio-Frequency
Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
J. Lescot, F.J.R. Cl´ement (Cadence Design Systems, Voiron, France)
Estimation of Crosstalk Noise for On-Chip Buses . . . . . . . . . . . . . . . . . . . . . 111
S. Tuuna, J. Isoaho (University of Turku, Finland)
A Block-Based Approach for SoC Global Interconnect Electrical
Parameters Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
M. Addino, M.R. Casu, G. Masera, G. Piccinini, M. Zamboni
(Politecnico di Torino, Italy)
Interconnect Driven Low Power High-Level Synthesis . . . . . . . . . . . . . . . . . . 131
A. Stammermann, D. Helms, M. Schulte, A. Schulz, W. Nebel (OFFIS
Research Institute,Oldenburg,Germany)
Asynchronous Techniques
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap . . . 141
J. Kessel, A. Peeters, S.-J. Kim (Philips Research
Laboratories,Eindhoven,Germany)
Power-Consumption Reduction in Asynchronous Circuits Using Delay
Path Unequalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
S. L´opez, O. Garnica, J.I. Hidalgo, J. Lanchares, R. Hermida
(Universidad Complutense de Madrid, Spain)
New GALS Technique for Datapath Architectures . . . . . . . . . . . . . . . . . . . . . 161
M. Krsti´c, E. Grass (IHP Microelectronics, Frankfurt, Germany)
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders . . . 171
J.L. Fragoso, G. Sicard, M. Renaudin
(TIMA Laboratory, Grenoble, France)
Statistic Implementation of QDI Asynchronous Primitives . . . . . . . . . . . . . . 181
The Emergency of Design for Energy Efficiency: An EDA Perspective . . . 192
A. Domic (Synopsys, Inc., Mountain View, USA)
Industrial Session
The Most Complete Mixed-Signal Simulation Solution with
ADVance MS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
J. Oudinot (Mentor Graphics, Meudon La Foret, France)
Signal Integrity and Power Supply Network Analysis of Deep
SubMicron Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
L.K. Scheffer (Cadence Design Systems, USA)
Power Management in Synopsys Galaxy Design Platform . . . . . . . . . . . . . . 195
Synopsys, Inc., Mountain View, USA
Open Multimedia Platform for Next-Generation Mobile Devices . . . . . . . . 196
STMicroelectronics, Agrate Brianza, Italy
RTL Power Modeling and Memory Optimisation
Statistical Power Estimation of Behavioral Descriptions . . . . . . . . . . . . . . . . 197
B. Arts, N. van der Eng, M. Heijligers, H. Munk, F. Theeuwen (Philips
Research Laboratories, Eindhoven, The Netherlands),
L. Benini (Universit`a di Bologna, Italy), E. Macii, A. Milia, R. Maro,
A. Bellu (Politecnico di Torino, Italy)
A Statistic Power Model for Non-synthetic RTL Operators . . . . . . . . . . . . . 208
M. Bruno (BullDast s.r.l), A. Macii (Politecnico di Torino, Italy),
M. Poncino (Universit`a di Verona, Italy)
Energy Efficient Register Renaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
G. Kucuk, O. Ergin, D. Ponomarev, K. Ghose (SUNY Binghamton,
USA)
Stand-by Power Reduction for Storage Circuits . . . . . . . . . . . . . . . . . . . . . . . 229
S. Cservany, J.-M. Masgonty, C. Piguet (CSEM, Switzerland)
A Unified Framework for Power-Aware Design of Embedded Systems . . . . 239
J.L. Ayala, M. Lopez-Vallejo (Universidad Politecnica de Madrid, Spain)
High-Level Modeling
A Flexible Framework for Fast Multi-objective Design Space Exploration
of Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
High Level Area and Current Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Fei Li, Lei He (UCLA, USA), Joe Basile, Rakesh J. Patel,
Hema Ramamurthy (Intel Corporation, USA)
Switching Activity Estimation in Non-linear Architectures . . . . . . . . . . . . . 269
A. Garc´ıa-Ortiz, L. Kabulepa, M. Glesner (Institute of Microelectronic
Systems, Mstad, Germany)
Instruction Level Energy Modeling for Pipelined Processors . . . . . . . . . . . . 279
S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas
(Aristotele University of Thessaloniki, Greece)
Power Estimation Approach of Dynamic Data Storage on a
Hardware Software Boundary Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
M. Leeman, D. Atienza, F. Catthoor, V. De Florio, G. Deconinck,
J.M. Mendias, R. Lauwereins (ESAT, Belgium)
Power Efficient Technologies and Designs
An Adiabatic Charge Pump Based Charge Recycling Design Style. . . . . . . 299
V. Manne, A. Tyagi (Iowa State University, USA)
Reduction of the Energy Consumption in Adiabatic Gates by Optimal
Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
J. Fischer, E. Amirante, F. Randazzo, G. Iannaccone,
D. Schmitt-Landsiedel (Institute for Technical Electronics,
Technical University M¨unich, Germany)
Low Power Response Time Accelerator with Full Resolution for
LCD Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung,
Soo-Won Kim (Samsung Electronics Co.Ltd, Korea)
Memory Compaction and Power Optimization for
Wavelet-Based Coders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
V. Ferentinos, M. Milia, G. Lafruit, J. Bormans, F. Catthoor
(IMEC-DESICS, Belgium)
Design Space Exploration and Trade-Offs in Analog Amplifier Design . . . . 338
E. Hjalmarson, R. H¨agglund, L. Wanhammar (Linkoping University,
Sweden)
Keynote Speech
Power and Timing Driven Physical Design Automation . . . . . . . . . . . . . . . . 348
Communication Modeling and Design
Analysis of Energy Consumed by Secure Session Negotiation Protocols in
Wireless Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
R. Karri, P. Mishra (Polytechnic University, New York, USA)
Remote Power Control of Wireless Network Interfaces . . . . . . . . . . . . . . . . . 369
A. Acquaviva, T. Simunic, V. Deolalikar, S. Roy (Universit`a di Urbino,
Italy)
Architecture-Driven Voltage Scaling for High-Throughput
Turbo-Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
F. Gilbert, N. When (University of Kaiserslautern, Germany)
A Fully Digital Numerical-Controlled-Oscillator . . . . . . . . . . . . . . . . . . . . . . . 389
Seyed Reza Abdollahi (Mazandaran, Iran), B. Bakkaloglu
(Texas Instrument, USA), S.K. Hosseini
(Iran Marine Industry, Iran)
Low Power Issues in Processors and Multimedia
Energy Optimization of High-Performance Circuits . . . . . . . . . . . . . . . . . . . . 399
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija (University of
California, USA)
Instruction Buffering Exploration for Low Energy Embedded Processors . 409
T. Vander Aa, M. Jayapala, F. Barat, G. Deconinck,
R. Lauwereins, H. Corporaal, F. Catthoor, (ESAT/ELECTA, Belgium)
Power-Aware Branch Predictor Update for High-Performance Processors . 420
A. Baniasadi (University of Victoria, Canada)
Power Optimization Methodology for Multimedia Applications
Implementation on Reconfigurable Platforms . . . . . . . . . . . . . . . . . . . . . . . . . 430
K. Tatas, K. Siozios, D.J. Soudris, A. Thanailakis
(Democritus University of Thrace, Greece), K. Masselos,
K. Potamianos, S. Blionas (Intracom SA, Greece)
High-Level Algorithmic Complexity Analysis for the Implementation of a
Motion-JPEG2000 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
M. Ravasi, M. Mattavelli (Swiss Federal Institute of Technology,
Switzerland, Greece), P. Schumacher, R. Turney
(Xilinx Research Labs, USA)
Poster Session 1
Metric Definition for Circuit Speed Optimization . . . . . . . . . . . . . . . . . . . . . . 451
Optical versus Electrical Interconnections for Clock Distribution Networks
in New VLSI Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
G. Tosik, F. Gaffiot, Z. Lisik, I. O’Connor, F. Tissafi-Drissi
(Ecole Centrale de Lyon, France)
An Asynchronous Viterbi Decoder for Low-Power Applications . . . . . . . . . 471
B. Javadi, M. Naderi, H. Pedram, A. Afzali-Kusha, M.K. Akbari
(Amirkabir University of Technology, Iran)
Analysis of the Contribution of Interconnect Effects in the
Energy Dissipation of VLSI Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
E. Isern, M. Roca, F. Moll (Universitat Illes Balears, Spain)
A New Hybrid CBL-CMOS Cell for Optimum
Noise/Power Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
R. Jim´enez, P. Parra, P. Sanmart´ın, A.J. Acosta
(IMSE-CNM/Universidad de Sevilla/Universidad de Huelva, Spain)
Computational Delay Models to Estimate the Delay of Floating Cubes in
CMOS Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
D. Guerrero, G. Wilke, J.L. G¨untzel, M.J. Bellido, J.J. Chico,
P. Ruiz-de-Clavijo, A. Millan (IMSE-CNM/Universidad de Sevilla,
Spain)
Poster Session 2
A Pratical ASIC Methodology for Flexible Clock Tree Synthesis with
Routing Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Dongsheng Wang, P. Suaris, Nan-chi Chou
(Mentor Graphics Corporation, Oregon, USA)
Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus . . . . . . 520
Byung-Soo Choi, Dong-Ik Lee (Kwangju Insitute of Science and
Technology, South Korea)
Reducing Static Energy of Cache Memories via Prediction-Table-Less
Way Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Akihito Sakanaka, Toshinori Sato (U. Fukuoka, Japan)
A Bottom-Up Approach to On-Chip Signal Integrity . . . . . . . . . . . . . . . . . . 540
A. Acquaviva, A. Bogliolo (Universit`a di Urbino, Italy)
Advanced Cell Modeling Techniques Based on Polynomial Expressions . . . 550
Wen-Tsong Shiue, Weetit Wanalertlak (Oregon State University, USA)
RTL-Based Signal Statistics Calculation Facilitates Low Power
Design Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Poster Session 3
Data Dependences Critical Path Evaluation at C/C++ System
Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
A. Prihozhy, M. Mattavelli, D. Mlynek (Ecole Polytechnique Federal de
Lausanne, Switzerland)
A Hardware/Sofware Partitioning and Scheduling Approach for Embedded
Systems with Low-Power and High Performance Requirements . . . . . . . . . . 580
J. Resano, D. Mozos, E. P´erez, H. Mecha, J. Septi´en (Universidad
Complutense de Madrid, Spain)
Consideration of Control System and Memory Contributions in Pratical
Resource-Constrained Scheduling for Low Power . . . . . . . . . . . . . . . . . . . . . . 590
Chee Lee, Wen-Tsong Shiue (Oregon State University, USA)
Low Power Cache with Successive Tag Comparison Algorithm . . . . . . . . . . 599
Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
(Samsung, Kyunggi-Do, Korea)
FPGA Architecture Design and Toolset for Logic Implementation . . . . . . . 607
K. Tatas, K. Siozios, N. Vasiliadis, D.J. Soudris, S. Nikolaidis,
S. Siskos, A. Thanailakis (Democritus University of Trace, Greece)
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis . 617
M.C. Molina, R. Ruiz-Sautua, J.M. Mendias, R. Hermida
(Universidad Complutense de Madrid, Spain)
Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

mscyc0909

Take a look! 3/3#

lf_0215

这个会议很好的，谢谢楼主！

lf_0215

谢谢楼主共享这种好资料！

lf_0215

感谢楼主的共享，继续努力！！

wanglixu2005

谢谢分享，最近刚刚接触timing。