IC & System Design 2003 - Power&Timing Modeling,Optimization....

lotusky

Integrated Circuit and System Design - Power and Timing Modeling,Optimization and Simulation

13th InternationalWorkshop, PATMOS 2003
Turin, Italy, September 10-12, 2003
Proceedings

Edited by G. Goos, J. Hartmanis, and J. van Leeuwen

[ 本帖最后由 lotusky 于 2007-12-29 16:01 编辑 ]

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Preface

Welcome to the proceedings of PATMOS 2003. This was the 13th in a series
of international workshops held in several locations in Europe. Over the years,
PATMOS has gained recognition as one of the major European events devoted
to power and timing aspects of integrated circuit and system design. Despite its
significant growth and development, PATMOS can still be considered as a very
informal forum, featuring high-level scientific presentations together with open
discussions and panel sessions in a free and relaxed environment.
This year, PATMOS took place in Turin, Italy, organized by the Politecnico
di Torino, with technical co-sponsorship from the IEEE Circuits and Systems
Society and the generous support of the European Commission, as well as that
of several industrial sponsors, including BullDAST, Cadence, Mentor Graphics,
STMicroelectronics, and Synopsys.
The objective of the PATMOS workshop is to provide a forum to discuss and
investigate the emerging problems in methodologies and tools for the design of
new generations of integrated circuits and systems. A major emphasis of the
technical program is on speed and low-power aspects, with particular regard to
modeling, characterization, design, and architectures.
A total of 85 contributed papers were received. Many thanks to all the authors
that submitted their contributions. In spite of a very dense technical program,
we were able to accept only 43 regular papers and 18 posters. Posters differ from
regular papers in that they are presented to the audience during three sessions
in which authors stand by cardboard displays and answer questions. Authors of
regular papers, instead, deliver traditional oral presentations of their contributions
during the sessions of the technical program.
Three keynote talks, offered by leading experts from industry and academia,
served as starters for the three days of the workshop: Dr. Andrea Cuomo, Corporate
VP of STMicroelectronics, Dr. Antun Domic, Senior VP of Synopsys
Inc., and Dr. Ricardo Reis, Professor at the Universidad Federal Rio Grande do
Sul addressed hot issues regarding architectures for next generation integrated
platforms, EDA tools for energy-efficient design, and physical synthesis for highspeed
and low-power circuits, respectively.
An industrial session, in which scientists from EDA and IC manufacturing companies
illustrated their most recent advances in R&D activities and leading-edge
technology development complemented the technical program.
Finally, a one-hour panel session took advantage of the presence of Officers from
the European Commission and Coordinators of large EU-funded collaborative
projects to provide insights into the new instruments and mechanisms now available
in Europe for supporting research and innovation activities.
Last, but not least, a rich social program, paired with an industrial exhibition,
guaranteed additional opportunities for establishing new relationships among
the workshop participants.
VI Preface
Many thanks to the technical program committee for all their hard work in paper
review, paper selection, and session organization. Additional experts also collaborated
in the review process, and we acknowledge their contribution. Lists of
technical program committee members and of additional reviewers can be found
the following pages. Thanks also to the invited speakers for graciously donating
their time and to the panelists for an enlightening and entertaining session.
We hope you found the workshop both stimulating and helpful and that you will
enjoyed your stay in Turin for the whole duration of the event.
September 2003

Jorge Juan Chico
Enrico Macii

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