modelsim problem,help!!

friday

I use input I/O, everything is ok, but after I change it to bidirectional I/O, in modelsim pe 5.5, it shows the red signal which means undefined, who can tell me why and how to deal with it.
thanks

bravelu

双向口要用三态门来控制，否则会有数据冲突（红色除了代表信号为定义，也可以是数据冲突）。code可以贴出来看看么？

friday

thanks, bravelu
but I am not clear about how to use three-states gate to control the bidirectional port?
can you give me a sample?  phoenix-y@sohu.com
thanks a lot!

bravelu

module bidir
(
clk,
direc, // direction of data;
data
);
input clk;
input direc;
inout [7:0] data;
wire clk;
wire direc;
wire [7:0] data;
reg [7:0] data_tmp;
reg [7:0] target_reg; // this is the internal register you want to read or write.
assign data = direc?data_tmp:8'hzz;
always@(posedge clk)
begin
  if(direc)
      data_tmp<=target_reg;
  else
      target_reg<=data;
end
endmodule