vivado [Labtools 27-3412]错误怎么解决？

白无常

[Labtools 27-3412] Mismatch between the design programmed into the device 'xc7a100t' (JTAG device index = '0'
and the probes file(s) 'E:/verilog/FRE_DEC/FRE_DEC.runs/impl_1/debug_nets.ltx'.
The hw_probe '<const0>' in the probes file has port index '15'. This port location for the ILA core at location (uuid_23E7D65A79BC59F7BC47406C1714DFAE), does not support a data probe.
.
Resolution:
1) Ensure that the clock signal connected to the debug core and/or debug hub is clean and free-running.
2) Ensure that the clock connected to the debug core and/or debug hub meets all timing constraints.
3) Ensure that the JTAG clock frequency is 2.5x times slower than the frequency of the clock connected to your debug hub.

这种问题怎么解决，我已经检查过了，时钟没有问题啊JTAG也是之前用的，之前的代码是对的，新项目就不对

susezeng

我也遇到同样的问题，我把JTAG的时钟降下来就可以烧bit了，但是感觉烧进去过后，板子状态不对。程序在其他板子上验证过的，请问老师，最后你是怎么解决的呢？为什么会报这个错误弄清楚了吗？这两天我也在排查原因