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module seq_fsm(
input din,clk,rst_n,
output cout,
output reg [2:0]current_state,next_state
);
parameter S0=000,
S1=001,
S2=010,
S3=011,
S4=100,
S5=101,
S6=110;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
current_state<=S0;
end
else begin
current_state<=next_state ;
end
end
always@(*) begin
case(current_state)
S0:begin if(din==1'b1)
begin next_state=S1; end
else begin next_state=S0;end
end
S1:begin if(din==1'b1)
begin next_state=S2;end
else begin next_state=S0;end
end
S2:begin if(din==1'b1)
begin next_state=S3; end
else begin next_state=S0;end
end
S3:begin if(din==1'b0)
begin next_state=S4;end
else begin next_state=S3;end
end
S4:begin if(din==1'b0)
begin next_state=S5; end
else begin next_state=S1;end
end
S5:begin if(din==1'b1)
begin next_state=S6;end
else begin next_state=S0;end
end
S6:begin if(din==1'b0)
begin next_state=S0;end
else begin next_state=S2;end
end
default:next_state=S0;
endcase
end
assign cout=((current_state==S6)&&(din==1'b0))? 1:0;
endmodule
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