RTL Design Style Guide for Verilog HDL

kylkzy · 发表于 2019-4-23 10:35:44

Chapter 1, Basic Design Constraints, describes general design restrictions you should consider
before you begin your design, such as naming conventions, design styles, clocking schemes, synchronous
and asynchronous design considerations, hierarchical design philosophies, and so on.
Chapter 2, RTL Description Techniques, discusses basic RTL coding styles and techniques designers
can apply to their designs. Also demonstrates coding styles for combinational and sequential
logic, as well as how to use the always, function, if, case and other statements.
Chapter 3, RTL Design Methodology, describes how to create function libraries, parameterize
design resources, insert design-for-test (DFT) structures, implement low-power design techniques,
manage design data and so on. Following the rules and recommendations set forth in this chapter
improves reusability of your design resources.
Chapter 4, Verification Techniques, introduces simulation techniques, including how to parameterize
testbenches, how to use tasks, how to draw up a verification strategy, and so on.
Appendix A-5, Logic Synthesis Using Design Compiler, contains tips and hints for using logic
synthesis tools.