求教，vcs混合仿真，glbl.v文件编译进默认库，为何找不到 ？

american007

使用默认的库映射：
-- Default workspace (Current dir)
---------------------------------------------------------------
WORK                            > DEFAULT
DEFAULT                         : .
然后执行下面两条命令

[lq@simuhost vcs]$vlogan -full64 -sverilog +v2k -f filelist_verilog.v +incdir+../../../imports +incdir+../../../MIG_OV_PRG.srcs/sources_1/ip/clk_wiz_sys +incdir+../../../MIG_OV_PRG.srcs/sources_1/ip/clk_wiz_hdmi  +define+GLBL ./glbl.v -l verilog.log



[lq@simuhost vcs]$ vcs -full64 -fsdb -top  WORK.sim_tb_top WORK.glbl -l vcs.log -o simv1
Doing common elaboration
                         Chronologic VCS (TM)
         Version H-2013.06_Full64 -- Thu Dec 27 17:42:41 2018
               Copyright (c) 1991-2013 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Error-[TMENF-IL] Top Module/Entity not found
  Top module/entity/config "WORK.sim_tb_top" is not found in library
  "DEFAULT".


Error-[TMENF-IL] Top Module/Entity not found
  Top module/entity/config "WORK.glbl" is not found in library "DEFAULT".


Error-[NM] No modules defined
  No modules defined in current design file(s).  

3 errors
CPU time: .149 seconds to compile

common elaboration failed
哪里用错了 ？

jing0806forever

解决了吗

dignity

我也遇到这个问题，咋解