高价悬赏-后端设计数据案例

金海林

有偿寻求后端设计数据案例testcase用于教学

需要一个后端设计的案例数据。包含以下设计文件。价格面议。

1.
hierarchical gate_level verilog netlist files(multiple modules) *.v

2.
timing constraints file( Synopsys DesignConstraint file) *.sdc

3.
hierarchical interconnect RC spef files (multiple blocks ) *.spef

4.
Liberty timing library files (including delay,transition, must have power table) *.lib

5.
LEFfiles ( including lef technology file) *.lef

6.
hierarchicalDEF files ( must have POWER and GROUND nets) *.def

7.
VDDand GND pad location file

8.
InterconnectTechnology File ( ITF file)
*.itf
this file is from foundry such as TSMC 28nm

9.gate-level verilog simulation (value change dump) VCD file *.vcd