synopsys 2007新书《Low Power Methodology Manual》

clarkkevin

Table of Contents
Preface...........................................................................................xv
1 Introduction....................................................................................1
1.1 Overview ....................................................................................................... 1
1.2 Scope of the Problem..................................................................................... 2
1.3 Power vs. Energy........................................................................................... 3
1.4 Dynamic Power ............................................................................................. 4
1.5 The Conflict Between Dynamic and Static Power ........................................ 7
1.6 Static Power................................................................................................... 8
1.7 Purpose of This Book .................................................................................. 10
2 Standard Low Power Methods ...................................................13
2.1 Clock Gating................................................................................................ 13
2.2 Gate Level Power Optimization .................................................................. 15
2.3 Multi VDD................................................................................................... 16
2.4 Multi-Threshold Logic ................................................................................ 17
2.5 Summary of the Impact of Standard Low Power Techniques ..................... 19
3 Multi-Voltage Design ...................................................................21
3.1 Challenges in Multi-Voltage Designs.......................................................... 22
3.2 Voltage Scaling Interfaces – Level Shifters................................................. 22
3.2.1 Unidirectional Level Shifters ......................................................... 23
3.2.2
3.2.3
3.2.4
3.2.5 Automation and Level Shifters....................................................... 27
3.2.6 Level Shifter Recommendations and Pitfalls ................................. 28
3.3 Timing Issues in Multi-Voltage Designs ..................................................... 29
3.3.1 Clocks ............................................................................................. 29
3.3.2 Static Timing Analysis ................................................................... 30
3.4 Power Planning for Multi-Voltage Design .................................................. 30
3.5 System Design Issues with Multi-Voltage Designs..................................... 31
4 Power Gating Overview ..............................................................33
4.1 Dynamic and Leakage power profiles......................................................... 33
4.2
4.3 Principles of Power Gating Design ............................................................ 37
4.3.1 Power Switching ? Fine Grain vs. Coarse Grain............................ 38
4.3.2 The Challenges of Power Gating.................................................... 39
5 Designing Power Gating..............................................................41
5.1 Switching Fabric Design ............................................................................. 42
5.1.1 Controlling the Switching Fabric ................................................... 44
5.1.2
5.2
5.2.1 Signal Isolation techniques............................................................. 45
5.2.2 Output or Input Isolation ................................................................ 47
5.2.3 Interface Protocols and Isolation .................................................... 48
5.2.4 Recommendations and Pitfalls for Isolation................................... 50
5.3
5.3.1 State Retention Using Scan Chains ................................................ 51
5.3.2 Retention Registers......................................................................... 54
5.3.3 Power Controller Design for Retention.......................................... 56
5.3.4 Partial vs. Full State Retention ....................................................... 56
5.3.5 System Level Issues and Retention ................................................ 58
5.3.6
5.4
5.4.1
5.4.2 Handshake Protocols ...................................................................... 61
5.4.3
5.5
Level Shifters ? High to Low Voltage Translation......................... 23
Level Shifters ? Low-to-High Voltage........................................... 24
Level Shifter Placement ................................................................. 25
Impact of Power Gating on Classes of Sub-systems................................... 36
Recommendations and Pitfalls for Power Gating Control ............. 44
Signal Isolation .......................................................................................... 45
State Retention and Restoration Methods ................................................... 50
Recommendations and Pitfalls for State Retention ........................ 58
Power Gating Control.................................................................................. 59
Power Control Sequencing.............................................................. 60
Recommendations and Pitfalls for Power Gating Controllers ....... 63
Power Gating Design Verification ? RTL Simulation................................. 63

and so on

xlu

这可是好东西啊，不过我早有了

denap

Thanks for sharing!!

denap

Thanks for sharing!!

clarkkevin

不过我可是经过工作以后， 把里面很多垃圾信息删除掉了。
花了两个多小时呢。

LAS.xs

ding!

kaoruzhu

thanks

LAS.xs

ding!

Orange-c

Thanks.

俊雅

顶！！！！！！！