library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity cn_test is
port(
a,b: in std_logic;
con1a: out std_logic);
end cn_test;
architecture cn_test_behav of cn_test is
begin
process(a,b)
variable x:bit :='0' ;
begin
if a='0' and b='0' then --是这有问题吗??
if x='0' then
con1a<='1';
elsif x='1' then
con1a<='0';
end if;
X:=not x;
end if;
end process;
end cn_test_behav;