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A Cascaded Continuous-time sigma delta modulator (IEEE 2004)
IEEE Journal of Solid-State Circuits, vol. 39, pp. 2152 - 2160, December 2004
A cascaded continuous-time sigma delta modulator with 67-dB dynamic range in 10-MHz bandwidth
AUTHORS: Lucien J. Breems, Robert Rutten, and Gunnar Wetzker
ABSTRACT:
This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-µm CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.
[ 本帖最后由 lovawoody 于 2007-6-18 16:48 编辑 ] |
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