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发表于 2017-6-28 09:25:00
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回复 1# pandapigwtj
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:54:22 08/18/2016
// Design Name:
// Module Name: LMK
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LMK(
output sync, //Device control
output goe,
input lmk_ld,
output clk_wire, //Register control
output reg data_wire,
output reg le_wire,
input clk_4,
input rst1
);
assign clk_wire = clk_4;
parameter IDLE = 5'b0_0001,
SET_DATA = 5'b0_0010,
SEND_DATA= 5'b0_0100,
END_DATA = 5'b0_1000;
reg [4:0] state;
// Register Bit Value
localparam RESET_BIT = 1'b1;
localparam CLKOUT0_MUX = 2'h1; // divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT0_EN = 1'b0;//disabled
localparam CLKOUT0_DIV = 8'h10; //clock output divider value is 8
localparam CLKOUT0_DLY = 4'h0; //默认值0，无延迟，，，，， dly time
//R0 Bit
localparam CLKOUT1_MUX = 2'h1;// divided mode，相对于bypass模式增加了100ps的延时 // ADC Clock
localparam CLKOUT1_EN = 1'b1;//enabled
localparam CLKOUT1_DIV = 8'h10;// clock output divider value is 8
localparam CLKOUT1_DLY = 4'h0;//默认值0，无延迟
//R1 Bit
localparam CLKOUT2_MUX = 2'h1;// divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT2_EN = 1'b0;//disabled,备用
localparam CLKOUT2_DIV = 8'h20;//clock output divider value is 10
localparam CLKOUT2_DLY = 4'h0;//默认值0，无延迟
//R2 Bit
localparam CLKOUT3_MUX = 2'h1;// divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT3_EN = 1'b0;//disabled，备用
localparam CLKOUT3_DIV = 8'h20;//默认值，clock output divider value is 20
localparam CLKOUT3_DLY = 4'h0;//延时150ps，divided mode下有效
//R3 Bit
localparam CLKOUT4_MUX = 2'h1;//默认，bypassed mode，无延时
localparam CLKOUT4_EN = 1'b0;//disabled
localparam CLKOUT4_DIV = 8'h20;//默认值，clock output divider value is 10
localparam CLKOUT4_DLY = 4'h0;//默认值0，无延迟
//R4 Bit
localparam CLKOUT5_MUX = 2'h1;// divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT5_EN = 1'b0;//disabled
localparam CLKOUT5_DIV = 8'h5;//默认值，clock output divider value is 2
localparam CLKOUT5_DLY = 4'h0;//默认值0，无延迟
//R5 Bit
localparam CLKOUT6_MUX = 2'h1;// divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT6_EN = 1'b0;//disabled
localparam CLKOUT6_DIV = 8'h5;//默认值，clock output divider value is 4
localparam CLKOUT6_DLY = 4'h0;//默认值0，无延迟
//R6 Bit
localparam CLKOUT7_MUX = 2'h0;// divided mode，相对于bypass模式增加了100ps的延时
localparam CLKOUT7_EN = 1'b0;//disabled
localparam CLKOUT7_DIV = 8'h5;//默认值，clock output divider value is 6
localparam CLKOUT7_DLY = 4'h0;//默认值0，无延迟
//R7 Bit
localparam VBOOST = 1'b0;//不编程时默认值为0，enabled时，所有输出时钟的输出电压增加，噪声也增加
//R9 Bit
localparam DIV4 = 1'b1;//以防相位检测器频率高于20MHz,若高于除以4
//R11 Bit
localparam OSCIN_FREQ = 8'd100;//输入100MHz频率
localparam VCO_R4_LF = 3'h0;//默认，R4的值
localparam VCO_R3_LF = 3'h0;//默认，R3的值
localparam VCO_C3_C4_LF = 4'h0;//默认，c3,c4的值
//R13 Bit
localparam EN_FOUT = 1'b0;//默认，Fout引脚没有被使能
localparam EN_CLKOUT_GB = 1'b1;//默认
localparam POWERDOWN = 1'h0;//默认
localparam PLL_MUX = 4'd0;//LD引脚的输出模式为push—pull，功能是数字锁定检测
localparam PLL_R = 12'd100;//默认为10，PLL R Divider value is 2
//R14 Bit
localparam PLL_CP_GAIN = 2'h0;//默认
localparam VCO_DIV = 4'd2;//默认为2，VCO Divider value is 3
localparam PLL_N = 18'd750;//PLL N Divider value is 750，默认为760
//R15 Bit
// Fvoc=OSCIN_FREQ*PLL_N*VCO_DIV/PLL_R; 1500MHz
//
// Registers Configuration Value
parameter VAL_REG0 = {RESET_BIT, 12'h0, CLKOUT0_MUX, CLKOUT0_EN, CLKOUT0_DIV, CLKOUT0_DLY, 4'h0};//R0
parameter VAL_REG1 = {13'h0, CLKOUT1_MUX, CLKOUT1_EN, CLKOUT1_DIV, CLKOUT1_DLY, 4'h1}; //R1
parameter VAL_REG2 = {13'h0, CLKOUT2_MUX, CLKOUT2_EN, CLKOUT2_DIV, CLKOUT2_DLY, 4'h2}; //R2
parameter VAL_REG3 = {13'h0, CLKOUT3_MUX, CLKOUT3_EN, CLKOUT3_DIV, CLKOUT3_DLY, 4'h3}; //R3
parameter VAL_REG4 = {13'h0, CLKOUT4_MUX, CLKOUT4_EN, CLKOUT4_DIV, CLKOUT4_DLY, 4'h4}; //R4
parameter VAL_REG5 = {13'h0, CLKOUT5_MUX, CLKOUT5_EN, CLKOUT5_DIV, CLKOUT5_DLY, 4'h5}; //R5
parameter VAL_REG6 = {13'h0, CLKOUT6_MUX, CLKOUT6_EN, CLKOUT6_DIV, CLKOUT6_DLY, 4'h6}; //R6
parameter VAL_REG7 = {13'h0, CLKOUT7_MUX, CLKOUT7_EN, CLKOUT7_DIV, CLKOUT7_DLY, 4'h7}; //R7
parameter VAL_REG8 = 32'b0001_0000_0000_0000_0000_1001_0000_1000; //R8
parameter VAL_REG9 = {15'h5001, VBOOST, 16'h2a09}; //R9
parameter VAL_REG11 = {16'h82, DIV4, 15'hb}; //R11
parameter VAL_REG13 = {10'ha, OSCIN_FREQ, VCO_R4_LF, VCO_R3_LF, VCO_C3_C4_LF, 4'hd}; //R13
parameter VAL_REG14 = {3'h0, EN_FOUT, EN_CLKOUT_GB, POWERDOWN, 2'h0, PLL_MUX, PLL_R, 8'he}; //R14
parameter VAL_REG15 = {PLL_CP_GAIN, VCO_DIV, PLL_N, 8'hf}; //R15
assign sync = ~rst1; //同步引脚低电平有效，直接连至复位
assign goe = lmk_ld; //根据数据手册，两个引脚通常连在一起
reg [31:0] data = 32'h0;
reg [3:0] cnt1 = 4'h0; //寄存器计数
reg [4:0] cnt2 = 5'h0; //数据传输位数计数
//always @(negedge clk_4) //20170607_1727
always @(posedge clk_4 or negedge rst1)
begin
if (!rst1) begin //将rst1改为！rst1 20170607_1728
state <= IDLE;
le_wire <= 1'b1;
data_wire <= 1'b0;
cnt1 <= 4'h0;
cnt2 <= 5'h0;
data <= 32'h0;
end
else begin
(* FULL_CASE *) case(state)
IDLE: begin
le_wire <= 1'b1;
data_wire <= 1'b0;
cnt1 <= 4'h0;
cnt2 <= 5'h0;
data <= 32'h0;
state <= SET_DATA ;
end
SET_DATA : begin
le_wire <= 1'b0;
cnt2 <= 5'h0;
if (cnt1 == 4'h0) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG0; // Reset Chip
end
else if (cnt1 == 4'h1) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= {1'b0, VAL_REG0[30:0]}; // REG0
end
else if (cnt1 == 4'h2) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG1; // REG1
end
else if (cnt1 == 4'h3) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG2; // REG2
end
else if (cnt1 == 4'h4) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG3 ; // REG3
end
else if (cnt1 == 4'h5) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG4 ; // REG4
end
else if (cnt1 == 4'h6) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG5; // REG5
end
else if (cnt1 == 4'h7) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG6 ; // REG6
end
else if (cnt1 == 4'h8) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG7 ; // REG7
end
else if (cnt1 == 4'h9) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG8 ; // REG8
end
else if (cnt1 == 4'ha) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG9 ; // REG9
end
else if (cnt1 == 4'hb) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG11; // REG11
end
else if (cnt1 == 4'hc) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG13; // REG13
end
else if (cnt1 == 4'hd) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG14; // REG14
end
else if (cnt1 == 4'he) begin
cnt1 <= cnt1 + 1'b1; state <= SEND_DATA ;
data <= VAL_REG15; // REG15
end
else begin
state <= END_DATA;
end
end
SEND_DATA: begin
le_wire <= 1'b0;
data_wire <= data[31];
data <= {data[30:0], 1'b0};
cnt2 <= cnt2 + 1'b1;
if (&cnt2) begin
state <= SET_DATA;
cnt2 <= 5'h0;
le_wire <= 1'b1; //20170607_1722
end
else begin
state <= SEND_DATA;
end
end
END_DATA: begin
//le_wire <= 1'b1; // 20170607_1722
le_wire <= 1'b0;
data_wire <= 1'b0;
state <= IDLE; //20170607_1722
end
default: state <= IDLE;
endcase
end
end
endmodule
这里贴上配置这块芯片的代码 |
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