mc8051扩展外设试验

weisonwsc · 发表于 2017-4-22 19:33:06

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本帖最后由 weisonwsc 于 2017-4-22 19:41 编辑

mc8051官网上有FPGA实现demo例程，我就不多说了，现在讲一下我如何在此基础上进行外设扩展。整体思路：
mc8051顶层没有外设的接口，片外RAM接口封装在内部，最大支持64KB，其实大多数情况下不需要这么多，而且一般的FPGA也没有那么多资源，我们可以把内部片外RAM接口再分成两个接口，一个接口连接到外部ram上，另一个接口连到外设上。

##1
在mc8051_top.vhd文件端口声明加上外设接口

per_data_out: out std_logic_vector(7 downto 0);
per_data_in : in std_logic_vector(7 downto 0);
per_adr : out std_logic_vector(15 downto 0);
per_wr : out std_logic;

复制代码

##2
修改mc8051_top_struc.vhd文件，主要是实现内部片外RAM接口分成两个接口，这里我使用2k的片外ram,大家根据自己的情况修改

architecture struc of mc8051_top is
signal s_rom_adr: std_logic_vector(15 downto 0); -- Programmcounter =
-- ROM-adress
signal s_rom_data: std_logic_vector(7 downto 0); -- data input from ROM
signal s_ram_data_out: std_logic_vector(7 downto 0); -- data output to
-- internal RAM
signal s_ram_data_in: std_logic_vector(7 downto 0); -- data input from
-- internal RAM
signal s_ram_adr: std_logic_vector(6 downto 0); -- internal RAM-adress
signal s_ram_wr: std_logic; -- read (0)/write (1)
-- internal RAM
signal s_ram_en: std_logic; -- RAM-block enable
signal s_datax_o: std_logic_vector(7 downto 0); -- data output to
-- ext. RAM
signal s_datax_i: std_logic_vector(7 downto 0); -- data input from
-- ext. RAM
signal s_adrx_o: std_logic_vector(15 downto 0); -- ext. RAM-adress
signal s_wrx_o: std_logic; -- read (0)/write (1)
-- ext. RAM
signal s_rom_adr_sml: std_logic_vector(14 downto 0);
signal s_ramx_adr_sml: std_logic_vector(10 downto 0);
signal s_ramx_data_in: std_logic_vector(7 downto 0);
signal s_ramx_data_out:std_logic_vector(7 downto 0);
signal s_ramx_wr: std_logic;
signal per_sel : std_logic;
begin -- architecture structural
s_rom_adr_sml <= std_logic_vector(s_rom_adr(14 downto 0));
s_ramx_adr_sml <= std_logic_vector(s_adrx_o(10 downto 0));
s_ramx_data_out<= s_datax_o ;
s_ramx_wr <= s_wrx_o when std_logic_vector(s_adrx_o(15 downto 11))="00000" else '0' ;
per_adr <= s_adrx_o;
per_data_out <= s_datax_o ;
per_wr <= s_wrx_o when std_logic_vector(s_adrx_o(15 downto 11))/="00000" else '0' ;
process(clk,reset)
begin
if(reset='1') then per_sel<='0';
elsif(rising_edge(clk)) then
if std_logic_vector(s_adrx_o(15 downto 11))="00000" then per_sel<='0' ;
else per_sel<='1';
end if;
end if;
end process;
s_datax_i<= s_ramx_data_in when per_sel='0' else
per_data_in ;
i_mc8051_core : mc8051_core
port map(clk => clk,
reset => reset,
rom_data_i => s_rom_data,
ram_data_i => s_ram_data_out,
int0_i => int0_i,
int1_i => int1_i,
all_t0_i => all_t0_i,
all_t1_i => all_t1_i,
all_rxd_i => all_rxd_i,
p0_i => p0_i,
p1_i => p1_i,
p2_i => p2_i,
p3_i => p3_i,
p0_o => p0_o,
p1_o => p1_o,
p2_o => p2_o,
p3_o => p3_o,
all_rxd_o => all_rxd_o,
all_txd_o => all_txd_o,
all_rxdwr_o => all_rxdwr_o,
rom_adr_o => s_rom_adr,
ram_data_o => s_ram_data_in,
ram_adr_o => s_ram_adr,
ram_wr_o => s_ram_wr,
ram_en_o => s_ram_en,
datax_i => s_datax_i,
datax_o => s_datax_o,
adrx_o => s_adrx_o,
wrx_o => s_wrx_o);
-----------------------------------------------------------------------------
-- Hook up the general purpose 128x8 synchronous on-chip RAM.
i_mc8051_ram : mc8051_ram
port map ( clock => clk,
data => s_ram_data_in,
q => s_ram_data_out,
address => s_ram_adr,
wren => s_ram_wr,
clken => s_ram_en);
-- THIS RAM IS A MUST HAVE!!
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Hook up the (up to) 64kx8 synchronous on-chip ROM.
i_mc8051_rom : mc8051_rom_32k
port map ( clock => clk,
q => s_rom_data,
address => s_rom_adr_sml);
-- THE ROM OF COURSE IS A MUST HAVE, ALTHOUGH THE SIZE CAN BE SMALLER!!
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Hook up the (up to) 64kx8 synchronous RAM.
i_mc8051_ramx : mc8051_xram_2k
port map ( clock => clk,
data => s_ramx_data_out,
q => s_ramx_data_in,
address => s_ramx_adr_sml,
wren => s_ramx_wr);
-- THIS RAM (IF USED) CAN BE ON OR OFF CHIP, THE SIZE IS ARBITRARY.
-----------------------------------------------------------------------------
end struc;