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Mail to: helen.lin@availink.com Office Line: 028-81499225 Position:Verification Engineer Location: Chengdu Responsibility 1. Developverification plan according to the Chip/IP specification 2. Setup UVMverification environment 3. CreateConstrain Random test pattern and direct test pattern to verify DUT 4. Createfunctional coverage by assertion or coverage groups 5. Workclosely with RTL designer to assist in simulation debug/code coverage analysis
Qualification 1. Bachelor degree or above majored in EE or related 2. Basic knowledge if IC design, IC production flow 3. Familiar at least one of Perl, Python, Shellprogramming 4. 2 years of verification experience 5. Plus: experience in UVM, display system, and chip/SOC level verification 6. Good interpersonal and communication skill,teamwork, and good written English, self-motivated, quick learner. |