[招聘]中天联科AISIC 验证工程师

Helen-Availink

E-mail：helen.lin@availink.com

Position：Senior Verificaiton Engineer

       Responsibility

1.Develop verification plan according tothe Chip/IP specification

2.Setup UVM verification environment

3.Create Constrain Random test patternand direct test pattern to verify DUT

4.Develop UVM Interface VIPs

5.Create functional coverage byassertion or coverage groups

6.Work closely with RTL designer toassist in simulation debug/code coverage analysis

Qualification

1.Master/Bachelor degree on EE orrelated with 3+ year experience in verification ,2+ year experience on UVM

2.Familiar with Perl/Python, shellprogramming

3.Basic knowledge of IC design, ICproduction flow

4.Experience in display system or DDR isa plus

5.Experience in chip/SOC levelverification is a plus

6.Excellent interpersonal andcommunication skills, good teamwork adaptability, good written English skills,self-motivated.

wsguestc

:):)