encounter求助

sekong179 · 发表于 2016-5-16 17:47:09

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本帖最后由 sekong179 于 2016-5-17 17:06 编辑

自己使用encounter，发现inport Design的时候，有warning，
最后trial route正常了链接，但是NanoRoute——>route的时候，pin链接的线会断开。

NanoRoute-->route的时候回提示

warning （NRIG-39） Pin rx[y] doesn't have physical shapes!

求大神帮忙，谢谢！！！

Loading Lef file tcb018g3d3_280a/tcb018g3d3_6lm.lef...

Set DBUPerIGU to M2 pitch 1120.
Initializing default via types and wire widths ...

Loading Lef file tpz973gv_280a/tpz973gv_6lm.lef...

Loading Lef file tpz973gv_280a/antenna_6lm.lef...

**WARN: (SOCLF-58):    Cell 'PCI33DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PCI33SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PCI66DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PCI66SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB02DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB02SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB04DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB04SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB08DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB08SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB12DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB12SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB16DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB16SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB24DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDB24SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDD02DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDD02SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDD04DGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-58):    Cell 'PDD04SDGZ' has been found in DB so only antenna data will be loaded. Any other data will be skipped.

**WARN: (SOCLF-61):    Too many duplicated macros defined in lef file. See log file for complete list of names.

**WARN: (SOCLF-200): Pin 'VSSPST' in macro 'PVSS2DGZ' has no ANTENNAGATEAREA attribute defined.

**WARN: (SOCLF-200): Pin 'AVSS' in macro 'PVSS2ANA' has no ANTENNAGATEAREA attribute defined
.
**WARN: (SOCLF-200): Pin 'AVSS' in macro 'PVSS1ANA' has no ANTENNAGATEAREA attribute defined.

**WARN: (SOCLF-200): Pin 'AVDD' in macro 'PVDD2ANA' has no ANTENNAGATEAREA attribute defined.

**WARN: (SOCLF-200): Pin 'I' in macro 'ANTENNA' has no ANTENNAGATEAREA attribute defined.

Power Planner/ViaGen version 6.2.2 promoted on 11/03/2006.

viaInitial starts at Mon May 16 11:43:40 2016

viaInitial ends at Mon May 16 11:43:40 2016

Reading netlist ...

Backslashed names will retain backslash and a trailing blank character.

Reading verilog netlist 'tsmc18.v'

*** Memory Usage v0.114.2.3 (Current mem = 173.336M, initial mem = 59.469M)***

*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=173.3M)***

Set top cell to SPI_WaterItem.
Reading max timing library 'tcb018g3d3_280a/tcb018g3d3wc.lib' ...

No function defined for cell 'DCAP'. The cell will only be used for analysis.

No function defined for cell 'ANTENNA'. The cell will only be used for analysis.
read 391 cells in library 'tcb018g3d3wc'

Reading max timing library 'tpz973gv_280a/tpz973gvwc.lib' ...

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PCI33DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PCI33DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PCI33SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PCI33SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PCI66DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PCI66DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PCI66SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PCI66SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB02DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB02DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB02SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB02SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB04DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB04DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB04SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB04SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB08DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB08DGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'PDB08SDGZ' is not defined in the library

**WARN: (TECHLIB-436):  Attribute 'max_capacitance' on output/inout pin 'C' of cell 'PDB08SDGZ' is not defined in the library

**WARN: (TECHLIB-438):  Too many pins with attribute 'max_capacitance' not defined in the library 'tpz973gvwc'. Warning suppressed for this attribute for rest of the pins in

this library
No function defined for cell 'PVSS3DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS2DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS2ANA'. The cell will only be used for analysis.

No function defined for cell 'PVSS1DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS1ANA'. The cell will only be used for analysis.

No function defined for cell 'PVDD2POC'. The cell will only be used for analysis.

No function defined for cell 'PVDD2DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVDD2ANA'. The cell will only be used for analysis.

No function defined for cell 'PVDD1DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVDD1ANA'. The cell will only be used for analysis.

No function defined for cell 'PRCUT'. The cell will only be used for analysis.

**WARN: (SOCTS-282): Cell 'PRT24DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRT16DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRT12DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRT08DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRO24CDG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRO16CDG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRO12CDG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PRO08CDG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDXO03DG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDXO02DG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDXO01DG' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDUWDGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level shifter,

use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDUSDGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level shifter,

use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDUDGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level shifter,

use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT24DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT16DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT12DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT08DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT04DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

**WARN: (SOCTS-282): Cell 'PDT02DGZ' is not a level shifter cell but has 'input_signal_level' and 'output_signal_level' specified on pins. To mark this cell as level

shifter, use 'is_level_shifter' attribute.

read 129 cells in library 'tpz973gvwc'

Reading min timing library 'tcb018g3d3_280a/tcb018g3d3bc.lib' ...

No function defined for cell 'DCAP'. The cell will only be used for analysis.

No function defined for cell 'ANTENNA'. The cell will only be used for analysis.

read 391 cells in library 'tcb018g3d3bc'

Reading min timing library 'tpz973gv_280a/tpz973gvbc.lib' ...

**WARN: (TECHLIB-438):  Too many pins with attribute 'max_capacitance' not defined in the library 'tpz973gvbc'. Warning suppressed for this attribute for rest of the pins in

this library
No function defined for cell 'PVSS3DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS2DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS2ANA'. The cell will only be used for analysis.

No function defined for cell 'PVSS1DGZ'. The cell will only be used for analysis.

No function defined for cell 'PVSS1ANA'. The cell will only be used for analysis.

read 129 cells in library 'tpz973gvbc'

*** End library_loading (cpu=0.08min, mem=38.2M, fe_cpu=0.11min, fe_mem=211.5M) ***

Starting recursive module instantiation check.

No recursion found.

Flattening Cell SPI_WaterItem ...

*** Netlist is unique.

** info: there are 1055 modules.

** info: there are 251 stdCell insts.

*** Memory Usage v0.114.2.3 (Current mem = 211.543M, initial mem = 59.469M) ***

Reading timing constraint file 'digital.sdc' ...

*info: set_input_delay : 6 accepted, 0 skipped!

*info: set_output_delay : 2 accepted, 0 skipped!

*info: set_load/set_capacitance : 162 accepted, 0 skipped!

*info: set_clock_transition : 4 accepted, 0 skipped!

*info: set_false_path : 1 accepted, 0 skipped!

*info: set_clock_uncertainty : 1 accepted, 0 skipped!

*info: create_clock : 1 accepted, 0 skipped!

*info: set_operating_conditions : 1 accepted, 0 skipped!

*info: set_wire_load_mode : 1 accepted, 0 skipped!

*Info: refer to log file for more detail on skipped constraints if any

Suppress "**WARN ..." messages.

Un-suppress "**WARN ..." messages.

**WARN: (TCLCMD-1013):  The SDC set_operating_conditions assertion is not supported. Please use the Encounter setOpCond command to specify library and operating condition

information. Use the setAnalysisMode command to control single vs. bestCase/worstCase vs. on-chip variation timing analysis. (File .constr.5443.pt, Line 4).

**WARN: (TCLNL-304): Pin 'scl' is a clock pin , data assertion ignored.  Use remove_assertion to remove previous assertion (File .constr.5443.pt, Line 424).

**WARN: (TCLNL-304): Pin 'scl' is a clock pin , data assertion ignored.  Use remove_assertion to remove previous assertion (File .constr.5443.pt, Line 426).

Number of path

exceptions in the constraint file = 1

Number of paths exceptions after getting compressed = 1

INFO (CTE): read_dc_script finished with  3 WARNING

*** Read timing constraints (cpu=0:00:00.0 mem=213.3M) ***

*info - Done with setDoAssign with 0 assigns removed and 0 assigns could not be removed.

*info: set bottom ioPad orient R0

Reading IO assignment file "../1/aaa.io" ...

WARNING (SOCFP-3007): Running I/O placement version 0 soon to be obsolete.

INFO: Using saveIoFile to convert I/O file into new format.

Set Using Default Delay Limit as 1000.

Set Default Net Delay as 1000 ps.

Set Default Net Load as 0.5 pF.

**WARN: (SOCDC-1159): Input Transition Time will be transferred from 0ps to 0.1ps.

Set Input Pin Transition Delay as 0.1 ps.