|
楼主 |
发表于 2016-1-28 20:39:45
|
显示全部楼层
回复 5# linghuqiubai 但是会报错。这样修改后又会出现如下错误。整个过程如下:我在ISE中建立了一个工程,其中用到了mig IP核,将整个工程作为一个外设挂在EDK下,其中综合时会报错The I/O component has an illegal IOSTANDARD value. The IOB component is configured to use single-ended signaling and can not use differential IOSTANDARD value DIFF_SSTL18_II_DCI. Two ways to rectify this issue are: 1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O connectivity by instantiating a differential I/O buffer.
ddr2_dqs和ddr2_dqs_n的所有信号都会报此错误。该工程在ISE中综合时并没有任何问题。其中设计这两个信号的地方为
module ddr2_phy_dqs_iob
IOBUFDS u_iobuf_dqs
(
.O (dqs_ibuf),
.IO (ddr_dqs),
.IOB (ddr_dqs_n),
.I (dqs_out),
.T (dqs_oe_n_r)
);
它的上一层文件中
genvar dqs_i;
generate
for(dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i+1) begin: gen_dqs
ddr2_phy_dqs_iob #
(
.DDR_TYPE (DDR_TYPE),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP)
)
u_iob_dqs
(
.clk0 (clk0),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.dlyinc_dqs (dlyinc_dqs[dqs_i]),
.dlyce_dqs (dlyce_dqs[dqs_i]),
.dlyrst_dqs (dlyrst_dqs),
.dlyinc_gate (dlyinc_gate[dqs_i]),
.dlyce_gate (dlyce_gate[dqs_i]),
.dlyrst_gate (dlyrst_gate[dqs_i]),
.dqs_oe_n (dqs_oe_n),
.dqs_rst_n (dqs_rst_n),
.en_dqs (en_dqs[dqs_i]),
.ddr_dqs (ddr_dqs[dqs_i]),
.ddr_dqs_n (ddr_dqs_n[dqs_i]),
.dq_ce (dq_ce[dqs_i]),
.delayed_dqs (delayed_dqs[dqs_i])
);
end
endgenerate
再上层文件是对其实例化ddr_dqs->ddr2_dqs
ddr2_dqs_n->ddr2_dqs_n
我的ucf中对信号的约束为
NET "ddr2_dqs" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "ddr2_dqs_n" IOSTANDARD = DIFF_SSTL18_II_DCI;
我搜了一些论坛的帖子,但是还么有找到解决的办法。请问您觉得这种错误会是什么原因?
|
|
|