ISE综合VHDL时报错 “Second argument of write must have a constant value”

322512lu

这个模块的代码如下。应该是完成读写文件功能的吧，用ISE14.2综合时报错，提示红色那一行“Second argument of write must have a constant value”。 因为对VHDL不熟悉，不知道该如何debug，请各位帮帮忙。应该怎么修改？谢谢！

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.dfp_parameters.all;
use work.dfp_types.all;
use work.program.all;

entity textinout is
  port ( clock : in bit;     -- WiGGL interface
        location : in Cell;
        writesig : in bit;
        datai : in Cell;
        datao : out std_logic_vector(Cell'high downto 0));
end entity;

architecture behaviour of textinout is
  signal a : Cell_nat;
begin

  a <= morf(location);

-- store on rising clock edge
  process(clock)
    variable outbuf : string(1 to 80);
    variable oindex : natural range 1 to 80;
    variable inbuf : string(1 to 80);
    variable iindex : natural range 1 to 80;
    variable lo : line;
    variable c : natural;
  begin
    c := morf(datai);
    if clock = '1' and clock'event then
      if  a = sci_data  then
        if writesig = '1' then
          if c < 32 then
            outbuf(oindex) := NUL;
            oindex := 1;
            write(lo, outbuf);
            writeline (output, lo);
          else
            outbuf(oindex) := character'val(c);
            oindex := oindex + 1;
          end if;
        else
          if inbuf(iindex) = NUL then
            iindex := 1;
            readline(input, lo);
            read(lo, inbuf);
          end if;
          datao(7 downto 0) <= to_stdlogicvector(nat_to_bits(character'pos(inbuf(iindex))));
          iindex := iindex + 1;
        end if;
      end if;
    end if;
  end process;

-- map outputs to datao
  process(a)
  begin
    case a is
      when sci_rf =>
        datao <= (0 => '1', others => '0');
      when sci_te =>
        datao <= (0 => '1', others => '0');
      when others =>
        datao <= (others => 'Z');
    end case;
  end process;

end;