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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 14:06:16 08/19/2015
- // Design Name:
- // Module Name: uart_rx
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module uartrx(clk,
- rx,
- dataout,
- rdsig,
- dataerror,
- frameerror
- );
- input clk;
- input rx;
- output dataout;
- output rdsig;
- output dataerror;
- output frameerror;
-
- reg rxbuf;
- reg rxfall;
- reg idle;
- reg [7:0] cnt;
- reg receive;
- reg presult;
-
- localparam paritymode = 1'b0;
- localparam [3:0]
- hold = 4'b0000,
- prepare = 4'b0001,
- start = 4'b0010,
- data0 = 4'b0011,
- data1 = 4'b0100,
- data2 = 4'b0101,
- data3 = 4'b0110,
- data4 = 4'b0111,
- data5 = 4'b1000,
- data6 = 4'b1001,
- data7 = 4'b1010,
- checkout = 4'b1011,
- stop = 4'b1100;
-
- always @(posedge clk)
- begin
- rxbuf <= rx;
- rxfall <= rxbuf & (~rx);
- end
- always @(posedge clk)
- begin
- if(rxfall & (~idle))
- receive <= 1;
- else if(counter == 8'd168)
- receive <= 0;
- end
- always @(posedge clk or posedge receive)
- begin
- if(receive)
- current_state <= next_state;
- end
- always @(*)
- begin
- case(current_state)
- hold:beginif(receive == 1)
- next_state = prepare;
- else
- next_state = hold;end
- prepare:beginif(cnt == 8'd8)
- next_state = start;elsenext_state = prepare;end
- start:beginif(cnt == 8'd24)
- next_state = data0;elsenext_state = start;end
- data0:beginif(cnt == 8'd40)
- next_state = data1; elsenext_state = data0;end
- data1:if(cnt == 8'd56)
- next_state = data2;elsenext_state = data1;end data2:beginif(cnt == 8'd72)
- next_state = data3;elsenext_state = data2;end data3:beginif(cnt == 8'd88)
- next_state = data4;elsenext_state = data3;end data4:beginif(cnt == 8'd104)
- next_state = data5; elsenext_state = data4; end
- data5:beginif(cnt == 8'd120)
- next_state = data6;elsenext_state = data5;end data6:beginif(cnt == 8'd136)
- next_state = data7;elsenext_state = data6;end data7:beginif(cnt == 8'd152)
- next_state = checkout;elsenext_state = data7;end checkout:beginif(cnt == 8'd168)
- next_state = stop; elsenext_state = checkout; end
- stop:beginnext_state = hold;end default: next_state = hold;
- endcase
- end
- always @(posedge clk)
- begin
- case(next_state)
- hold:begin
- idle <= 0;
- cnt <= 0;
- rdsig <= 0;
- end
- prepare: begin
- idle <= 1'b0;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- end
- start:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- end
- data0:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[0] <= rx;
- presult <= paritymode^rx;
- end
- data1:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[1] <= rx;
- presult <= presult^rx;
- end
- data2:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[2] <= rx;
- presult <= presult^rx;
- end
- data3:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[3] <= rx;
- presult <= presult^rx;
- end
- data4:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[4] <= rx;
- presult <= presult^rx;
- end
- data5:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[5] <= rx;
- presult <= presult^rx;
- end
- data6:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b0;
- dataout[6] <= rx;
- presult <= presult^rx;
- end
- data7:begin
- idle <= 1'b1;
- cnt <= cnt + 8'b1;
- rdsig <= 1'b1;
- dataout[7] <= rx;
- presult <= presult^rx;
- end
- checkout:begin
- if(presult == rx)
- dataerror <= 1'b0;
- else
- dataerror <= 1'b1;
- cnt <= cnt+8'b1;
- rdsig <= 1'b1;
- idle = 1'b1;
- end
- stop:begin
- if(rx == 1'b1)
- frameerror <= 1'b0;
- else
- frameerror <= 1'b1;
- idle <= 1'b1;
- cnt <= cnt+8'b1;
- rdsig <= 1'b1;
- end
- endcase
- end
- endmodule
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