招聘验证工程师

Cissy_pq

本公司急招验证工程师，感兴趣可发送简历至cissy_pq@163.com(工作地点：北京、上海)
Senior Verification Engineer
Common:
1)
Familiar with system Verilog and UVM methodology
2)
Familiar with UNIX/Linux shell
3)
Familiar with Perl script
4)
Provide test plan basing on the design spec
5)
Setup the module level and chip level DV environment
6)
RTL simulation and netlist with timing simulation
7)
Implement the test cases basing test plan, and provide the test coverage
8)
Work with design team to repeat the failure case and find out root cause

飞扬紫百合

Which company? Please PM to me!

Cissy_pq

回复 2# 飞扬紫百合


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muyu8780

只社招吗？