上海外资公司招数字设计和验证工程师

399394127

Dear All,

We have two urgent positions for internal referral program. Please find the JD as below. 大家可以试试，简历可发到我邮箱 399394127@qq.com ，欢迎咨询～～

Video Design Engineer (*4)

Job Description:

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Specify micro-architecture spec for media processors.

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Design logic related to video compression in verilog and System Verilog.

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Verify design and debug in both RTL-level and gate-level.

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Synthesize and optimize RTL for timing, area and power.

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Perform static timing analysis, formal verification, and clock domain crossing check.

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Participate FPGA debug and bring up chip.

Requirements:

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MSEE/CE with work experience.

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Experience in video compression/decompression is desired.

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Good understanding of computer architecture, logic design, and VLSI design.

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Knowledge of System Verilog, Verilog, C, C++, Perl, and Tcl.

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Strong communication skills and good team player.

Verification engineer(*4)

Position Overview:

On this key position, you will be able to make significant contributions to define the verification scope, develop the verification infrastructure and verify the correctness of the design with your experience and brilliant idea. If you are aiming high and are passionate for challenges, we are cordially inviting you to join the team for the ride.

Responsibilities:

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Develop verification environment, including test bench and regression system creation, embed it in company customized design flow.

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Build test plan and verify the function of design, support gate level functional verification, run coverage and regression. Analyze coverage gaps and devise strategy to fill coverage holes.

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Work closely with different groups to review specification, improve verification plan and methodology, and ensure full test coverage.

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Interfacing EDA vendors for for modern verification methodology, assess vendors' design verification capabilities and convergence .

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Related documentation.   

Requirements:

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BSEE with 4+ (or MSEE with 2+) years experience in asic verification, complex SOC verification experience is preferred.

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Solid knowledge in verification methodology. Experience in verification using random stimulus along with functional coverage and assertion-based verification method. Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV, lower power verification flow with CPF/UPF.

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Experience in developing block and chip level test benches, test plan creation.

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Good at timing analysis, practical skill with gate-level simulation and debugging techniques.

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Strong script programming skills, such as Shell scripting, Perl and Tcl programming, to develop command scripts.

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Self-motivated to drive for excellence. Must be a team player, and be disciplined and well organized.

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Excellent communication skills, and be able to work under schedule pressure.

399394127

自己顶

399394127

大家快来看，不要错过，待遇不错，工作压力不大

399394127

我相信大家的眼光，职位有限，大家不要客气。