马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
JD为以下: Working as a part of a team, you will have some or all of the following responsibilities: § Reviewing design specifications, developing the verification strategy and test plan § Development of constrained random Verification Environments § Writing tests, sequences, functional coverage, assertions and mapping these to Test plan § Functional verification of the design to achieve verification goals § Develop testbench to aid verification work including bus fabric/assertions/checker/coverpoints. § Understand architecture and microarchitecture of the MIPS CPU Required Skills: § Strong microprocessor architecture and micro-architecture knowledge. § Good logic and RTL design skills. § Experienced with CPU design verification, debug, and testing methodologies. § Good knowledge of common test methods and techniques (ie: regression, functional, random, structural, emulation ...) § Experienced with building test environments, test benches, checkers, test vectors, assertions, coverage analysis § Strong communications skills and capability to describe in detail all aspects of design verification § Good programming and scripting skills, such as Verilog, System Verilog, assembler, Perl, Shell scripts, C, TCL, Windows Office, ...etc § Synopsys/Cadence/Mentor tool usage and waveform analysis § UVM based test environment setup Desirable Skills: § MIPS CPU knowledge
若感兴趣,请联系: T: +86 (0)755 82775693 M: +86 13826547216/+86 18565761882 或可以把简历发到: Peter.Zhou@ic-resources.com |