求大神帮忙看看程序问题出在哪？modelsim仿真后输出数据一直为红线U

Amanda_e

大神帮忙看看吧~感激不尽。以下为testbench程序：library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;

entity tb_med is
end tb_med;

architecture beh_tb of tb_med is

file input_file: text open read_mode is "input4tb.dat";
file output_file: text open write_mode is "output_tb.dat";

  component med_filter is
  port (
        clk: in std_logic;
        reset: in std_logic;
        data_in: in std_logic_vector(7 downto 0);
        data_out: out std_logic_vector(7 downto 0)
       );
  end component med_filter;

  signal data_in: std_logic_vector(7 downto 0);
  signal data_out: std_logic_vector(7 downto 0);

signal clk: std_logic := '0' ;
  signal reset: std_logic := '1';
  --signal data_valid: std_logic := '0';

  begin
    duv: med_filter
    port map (data_in => data_in,
              clk     => clk,
              reset   => reset,
              data_out => data_out
              );

    reset_gen: process
    begin
        for n in 0 to 3 loop
           wait until falling_edge(clk);
        end loop;
        reset <= '0' ;
    end process reset_gen;

    clock: process
      constant half_clock_period: time := 10 ns;  -- for 100MHz
    begin
      clk <= '1';
      wait for half_clock_period;
      clk <= '0';
      wait for half_clock_period;   
    end process clock;

process

variable inline, outline : line;
variable input : std_logic_vector(7 downto 0);
variable output : std_logic_vector(7 downto 0);

begin
  while not endfile(input_file) loop

if (reset = '1') then

data_in <= (others => '0');

else

readline(input_file, inline);

read(inline, input);

data_in <= input;

--data_valid <= '1';

output := data_out;
      write(outline, output);
      writeline(output_file, outline);

end if;
  wait until clk = '1';
  end loop;
  --if rising_edge(clk) then

  --end if;

end process;

end beh_tb;