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大家好,这两天在做Modelsim仿真时,每次在rst为高电平时出现不定态,一直没找到原因,请大家帮忙分析分析~
- module txu_load_part_fault (clk, rst, data_req, en, n91, n92, n132, n137, n138, control, n93, n94, n95, n96);
- input clk, rst, en, data_req;
- input n91, n92, n132, n137, n138;
- input [41:0] control;
- output n93, n94, n95, n96;
-
- DFFARX1_RVT_FAULT \state_reg[0] ( .D(n73), .CLK(clk), .RSTB(rst), .Q(n78), .QN(n7) , .control({control[0],control[1],control[2],control[3],control[4],control[5],control[6],control[7],control[8],control[9],control[10],control[11],control[12]}));
- DFFARX1_RVT_FAULT \state_reg[1] ( .D(n72), .CLK(clk), .RSTB(rst), .Q(n79), .QN(n6) , .control({control[13],control[14],control[15],control[16],control[17],control[18],control[19],control[20],control[21],control[22],control[23],control[24],control[25]}));
- NAND3X0_RVT_FAULT U106 ( .A1(n6), .A2(n78), .A3(n92), .Y(n93) , .control(control[26]));
- NAND3X0_RVT_FAULT U107 ( .A1(n138), .A2(n132), .A3(n93), .Y(n95) , .control(control[27]));
- NAND2X0_RVT_FAULT U108 ( .A1(n137), .A2(n95), .Y(n94) , .control(control[28]));
- OAI22X1_RVT_FAULT U109 ( .A1(n6), .A2(n94), .A3(n7), .A4(n95), .Y(n73) , .control({control[29],control[30],control[31]}));
- OA221X1_RVT_FAULT U110 ( .A1(n7), .A2(en), .A3(n7), .A4(data_req), .A5(n95), .Y(
- n96) , .control({control[32],control[33],control[34]}));
- OA221X1_RVT_FAULT U111 ( .A1(n6), .A2(n132), .A3(n79), .A4(n96), .A5(n137), .Y(n72) , .control({control[35],control[36],control[37]}));
- AO222X1_RVT_FAULT U94 ( .A1(n137), .A2(n78), .A3(n137), .A4(n79), .A5(n137), .A6(
- n91), .Y(n138) , .control({control[38],control[39],control[40],control[41]}));
- endmodule
-
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- //用到的基本门单元的定义:
- module DFFARX1_RVT_FAULT (D, CLK, RSTB, control, Q, QN);
- output Q, QN;
- input D, CLK, RSTB;
- input [12:0] control;
- reg notifier;
- wire [12:0] n;
- pullup (setb);
- saed32_dff_pos_lvt (Q_buf, D, CLK, RSTB, setb, notifier);
- buf (n[0], Q_buf);
- xor (Q, n[0], control[0]);
- not (n[1], Q_buf);
- xor (QN, n[1], control[1]);
- `ifdef TETRAMAX
- `else
- saed32_xbuf_lvt (RSTB_SDFCHK, RSTB, 1'b1);
- saed32_xbuf_lvt (D_SDFCHK, D, 1'b1);
- saed32_xbuf_lvt (CLK_D_SDFCHK, CLK_D, 1'b1);
- saed32_xbuf_lvt (CLK_nD_SDFCHK, CLK_nD, 1'b1);
- saed32_xbuf_lvt (nCLK_D_SDFCHK, nCLK_D, 1'b1);
- saed32_xbuf_lvt (nCLK_nD_SDFCHK, nCLK_nD, 1'b1);
- saed32_xbuf_lvt (RSTB_D_SDFCHK, RSTB_D, 1'b1);
- saed32_xbuf_lvt (RSTB_nD_SDFCHK, RSTB_nD, 1'b1);
- `endif
- not (n[2], D);
- xor (nD, n[2], control[2]);
- not (n[3], CLK);
- xor (nCLK, n[3], control[3]);
- and (n[4], CLK, D);
- xor (CLK_D, n[4], control[4]);
- and (n[5], CLK, nD);
- xor (CLK_nD, n[5], control[5]);
- and (n[6], nCLK, D);
- xor (nCLK_D, n[6], control[6]);
- and (n[7], nCLK, nD);
- xor (nCLK_nD, n[7], control[7]);
- and (n[8], RSTB, D);
- xor (RSTB_D, n[8], control[8]);
- and (n[9], RSTB, nD);
- xor (RSTB_nD, n[9], control[9]);
- buf (n[10], RSTB);
- xor (RSTB_i, n[10], control[10]);
- buf (n[11], RSTB_i);
- xor (CLK_check, n[11], control[11]);
- buf (n[12], RSTB_i);
- xor (D_check, n[12], control[12]);
- `ifdef TETRAMAX
- `else
- saed32_xbuf_lvt (CLK_DEFCHK, CLK_check, 1'b1);
- saed32_xbuf_lvt (D_DEFCHK, D_check, 1'b1);
- `endif
- endmodule
- module NAND2X0_RVT_FAULT (A1, A2, control, Y);
- output Y;
- input A1, A2, control;
- wire n;
- nand (n, A2, A1);
- xor (Y, n, control);
- endmodule
-
- module NAND3X0_RVT_FAULT (A1, A2, A3, control, Y);
- output Y;
- input A1, A2, A3, control;
- wire n;
- nand (n, A2, A1, A3);
- xor (Y, n, control);
- endmodule
- module OAI22X1_RVT_FAULT (A1, A2, A3, A4, control, Y);
- output Y;
- input A1, A2, A3, A4;
- input [2:0] control;
- wire [2:0] n;
- or (n[0], A4, A3);
- xor (g_1_out, n[0], control[0]);
- or (n[1], A2, A1);
- xor (g_1_out, n[1], control[1]);
- nand (n[2], g_1_out,g_2_out);
- xor (Y, n[2], control[2]);
- endmodule
- module OA221X1_RVT_FAULT (A1, A2, A3, A4, A5, control, Y);
- output Y;
- input A1, A2, A3, A4, A5;
- input [2:0] control;
- wire [2:0] n;
- or (n[0], A2, A1);
- xor (g_2_out, n[0], control[0]);
- or (n[1], A3, A4);
- xor (g_3_out, n[1], control[1]);
- and (n[2], A5, g_2_out, g_3_out);
- xor (Y, n[2], control[2]);
- endmodule
- module AO222X1_RVT_FAULT (A1, A2, A3, A4, A5, A6, control, Y);
- output Y;
- input A1, A2, A3, A4, A5, A6;
- input[3:0] control;
- wire [3:0] n;
- and (n[0], A1, A2);
- xor (g_1_out, n[0], control[0]);
- and (n[1], A3, A4);
- xor (g_2_out, n[1], control[1]);
- and (n[2], A5, A6);
- xor (g_3_out, n[2], control[2]);
- or (n[3],g_1_out,g_2_out,g_3_out);
- xor (Y, n[3], control[3]);
- endmodule
- primitive saed32_xbuf_lvt (o, i, dummy);
- output o;
- input i, dummy;
- table
- // i dummy : o
- 0 1 : 0 ;
- 1 1 : 1 ;
- x 1 : 1 ;
- endtable
- endprimitive
- primitive saed32_dff_pos_lvt (q, d, clk, rstb, setb, notifier);
- output q;
- input d, clk, rstb, setb, notifier;
- reg q;
- table
- // d clk rstb setb ntfr Q
- ? ? 0 ? ? : ? : 0 ; // RST dominate SET
- ? ? 1 0 ? : ? : 1 ; // SET is set
- ? ? 1 x ? : 0 : x ; // SET affect Q
- ? ? 1 x ? : 1 : 1 ; // Q=1,preset=X
- ? ? x 1 ? : 0 : 0 ; // Q=0,clear=X
- 0 (01) ? 1 ? : ? : 0 ; // Latch 0
- 0 * ? 1 ? : 0 : 0 ; // Keep 0 (D==Q)
- 1 (01) 1 ? ? : ? : 1 ; // Latch 1
- 1 * 1 ? ? : 1 : 1 ; // Keep 1 (D==Q)
- ? (1?) 1 1 ? : ? : - ; // ignore negative edge of clock
- ? (?0) 1 1 ? : ? : - ; // ignore negative edge of clock
- ? ? (?1) 1 ? : ? : - ; // ignore positive edge of RST
- ? ? 1 (?1) ? : ? : - ; // ignore posative edge of SET
- * ? 1 1 ? : ? : - ; // ignore data change on steady clock
- // ? ? ? ? * : ? : x ; // timing check violation
- endtable
- endprimitive
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