终端信息:
Loading db file '/eda/synopsys/syn/2012.06/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/syn/2012.06/libraries/syn/standard.sldb'
Loading link library 'gtech'
Loading verilog file '/home/klin/Desktop/qixin_lab/qixin_verilog_CODE/fsm_moore/fsm_moore.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Warning: Can't read link_library file 'your_library.db'. (UID-3)
Compiling source file /home/klin/Desktop/qixin_lab/qixin_verilog_CODE/fsm_moore/fsm_moore.v
dc.setup文件:
#######################################################
#
# dc_shell TcL startup script:
#
set designer "klin"
set company "QiXin"
#
# Some design environment variables:
#
set search_path "$search_path ../library"
#
# tc = Typical; bc = Best; wc = Worst:
set target_library typical.db
set link_library "* $target_library"
#
set symbol_library tsmc090.sdb
#
# ---------------------------------
#
# Set up a work library for this design in a subdirectory:
define_design_lib fsm_moore -path ./fsm_mooreSynth