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发表于 2015-4-30 20:20:06
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回复 4# alyssa_injd
设计里 主要有一些状态机,状态机 都是三段式编写的,还有一些 由状态机的状态和一些信号 利用组合逻辑,作为在 if else 的条件判断语句,之后 slave1 模块中,自己建立了个 reg [31:0] memory [0:65535]; 之后在做后仿真时 报告出这么几个问题:
1 WARNING:Xst:2170 - Unit master1 : the following signal(s) form a combinatorial loop:
lastbrstwr, nstate<2>, u_pop_Hwrite1_AND_37_o, nstate[3]_GND_2_o_equal_117_o,
lastbrstwr_lastbrstrd_OR_46_o, nstate<0>, nstate[3]_Hresp1[1]_AND_32_o.
2 WARNING:Xst:1710 - FF/Latch <Htrans1_0> (without init value) has a constant value of 0 in block <m1>. This FF/Latch will be trimmed during the optimization process.
3 WARNING:Xst:1710 - FF/Latch <Hresp1_1> (without init value) has a constant value of 0 in block <s1>. This FF/Latch will be trimmed during the optimization process.
4 WARNING:Xst:2404 - FFs/Latches <Hresp1<1:1>> (without init value) have a constant value of 0 in block <slave1>.
5 WARNING:Xst:1710 - FF/Latch <Htrans1_0> (without init value) has a constant value of 0 in block <master1>. This FF/Latch will be trimmed during the optimization process.
6 后仿仿真波形中,状态机,有几个状态 完全不是 我在设计中,所要的,我真不知道 是什么原因。
大神们,这几天 我都快崩溃啦 咋整 求指导
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