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这个是SPI读写操作
这个是首字节的定义
请问如何按照这个要求用Verilog来设计该SPI slave,网上有关基本找不到相关的SPI slave参考代码
主要存在这几个疑问:1、SPI从机除了主机发过来的同步时钟SCLK外,是否还需要另外一个输入时钟?我看见网上有关的从机代码都增加了clk,而且是用这个clk来检测SCLK的上升沿和下降沿,我的疑问是从机不就是直接用posedge SCLK就可以是实现检测到上升沿了吗?
代码如下:
- module SPI_Slave(
- clk, //system clock 50MHz
- SCK, SSEL, MOSI,MISO//SPI communication pin
- );
- input SCK, SSEL, MOSI;
- output MISO;
-
- // sync SCK to the FPGA clock using a 3-bits shift register
- reg [2:0] SCKr;
- always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
- wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
- wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
- // same thing for SSEL
- reg [2:0] SSELr;
- always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
- wire SSEL_active = ~SSELr[1]; // SSEL is active low
- wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
- wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
- // and for MOSI
- reg [1:0] MOSIr;
- always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
- wire MOSI_data = MOSIr[1];
- reg [2:0] bitcnt; // we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
- //-------------------receive data-------------------------------------------------
- reg byte_received; // high when a byte has been received
- reg [7:0] byte_data_received,rev_data;
- reg [7:0] byte_data_sent,sent_data;
- always @(posedge clk)
- begin
- if( SSEL_active )
- begin
- if(SSEL_startmessage)
- byte_data_sent <= sent_data;
- end
- if(~SSEL_active)
- begin
- bitcnt <= 3'b000;
- byte_data_sent <= 8'h00; // after that, we send 0s///////////
- end
- else
- if(SCK_risingedge)
- begin
- bitcnt <= bitcnt + 3'b001;
- byte_data_received <= {byte_data_received[6:0], MOSI_data}; // implement a shift-left
- //register (since we receive the data MSB first)
- byte_data_sent <= {byte_data_sent[6:0], 1'b0};///////////
- end
- end
- always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
- //-----------------------receive data---------------------
- always @(posedge clk)
- if(byte_received)
- begin
- rev_data <= byte_data_received;
- end
- //-----------------------send data----------------------
- assign MISO = byte_data_sent[7]; // send MSB first
- endmodule
复制代码
2、怎么区分接收的是数据还是地址?
3、由于首字节定义了通信模式和地址,刚开始时是怎么检测读写使能及地址的,是接收一位用一个状态机吗,然后用八个状态,还是用计数器来检测?
4、当接收完地址0时时怎么转换到读数据或者写数据操作,如果在片选信号一直使能的情况下这个转换状态肯定要用到一个时钟沿,那么这时数据传输的连贯性不就会被破坏了吗?
实在搞不懂,望同行们提供一些宝贵意见,万分感谢! |
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