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出现了2个问题:
1、程序没有出错,但是逻辑单元居然使用率为0,这是为什么?
2、按PS2键盘的时序,一帧为11,第一位不管,2到9为数据,读取,10校验,11是结束位也就是断码F0位,这样理解不知道对不对,我按这样的理解写的程序读不到正确的值。
================================顶层文件=======================================
module ps2_top (
input clk,
input rstn,
input ps2_clk,
input ps2_data,
output [3:0]led
);
wire [7:0]ps2_data_decode;
wire h2l_sig;
wire ps2_keyup_sig;
ps2_h2l_sig u1(
.clk(clk), //input clk, from top
.rstn(rstn), //input rstn, from top
.ps2_clk(ps2_clk), //input ps2_clk, from top
.h2l_sig(h2l_sig) //output h2l_sig
);
ps2_decode u2(
.clk(clk), // input clk, from top
.rstn(rstn), // input rstn, from rstn
.h2l_sig(h2l_sig), // input h2l_sig, from u1
.ps2_data_in(ps2_data), // input ps2_data_in, from top
.ps2_data_decode(ps2_data_decode), // output [7:0]ps2_data_decode,
.ps2_keyup_sig(ps2_keyup_sig) // output ps2_keyup_sig
);
ps2_led u3(
.clk(clk), // input clk, from top
.rstn(rstn), // input rstn, from top
.ps2_data_decode_in(ps2_data_decode), // input ps2_data_decode_in, from u2
.ps2_keyup_sig(ps2_keyup_sig), // input ps2_keyup_sig, from u2
.led(led) // output [3:0]led
);
endmodule
======================================高低电平检测模块==============================
module ps2_h2l_sig (
input clk,
input rstn,
input ps2_clk,
output h2l_sig
);
reg h2l_sig_pre;
reg h2l_sig_now;
always@(posedge clk or negedge rstn)
begin
if(!rstn==1)
begin
h2l_sig_pre<=1'b1;
h2l_sig_now<=1'b1;
end else
begin
h2l_sig_now<=ps2_clk;
h2l_sig_pre<=h2l_sig_now;
end
end
assign h2l_sig=(!h2l_sig_now)&h2l_sig_pre;
endmodule
=====================================键盘解码模块================================
module ps2_decode (
input clk,
input rstn,
input h2l_sig,
input ps2_data_in,
output [7:0]ps2_data_decode,
output ps2_keyup_sig
);
reg [7:0]temp_data;
reg [4:0]i;
reg keyup_sig;
always@(posedge clk or negedge rstn)
begin
if(!rstn==1)
begin
temp_data<=8'b0;
i<=0;
keyup_sig<=0;
end else
begin
case(i)
4'd0:
begin
if(h2l_sig)
begin
i<=i+1'b1;
end
end
4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8:
begin
if(h2l_sig)
begin
i<=i+1'b1;
temp_data[i-1]<=ps2_data_in;
end
end
4'd9,4'd10:
begin
if(h2l_sig)
begin
i<=i+1'b1;
end
end
4'd11:
begin
i<=0;
keyup_sig<=1;
end
endcase
end
end
assign ps2_data_decode=temp_data;
assign ps2_keyup_sig=keyup_sig;
endmodule
=======================================LED控制模块==========================
module ps2_led(
input clk,
input rstn,
input ps2_data_decode_in,
input ps2_keyup_sig,
output [3:0]led
);
reg [3:0]temp_led;
always@(posedge clk or negedge rstn)
begin
if(!rstn==1)
begin
temp_led<=4'b0001;
end else
begin
case(ps2_data_decode_in)
8'h1d: temp_led<={temp_led[2:0], temp_led[3]};
8'h22: temp_led<={temp_led[2:0], temp_led[3]};
endcase
end
end
assign led=temp_led;
endmodule |
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