用EDI做完tree之后,ckSynthesis -report reports/cts/clock.rpt里面看到的phase delay如下:
###############################################################
# Complete Clock Tree Timing Report
#
# CLOCK: clk
#
# Mode: clkRouteOnly
#
# Delay Corner information
# Analysis View : wc_cworst_func
# Delay Corner Name : dc_wc
# RC Corner Name : cworst_125c
# Analysis View : wcl_cworst_func
# Delay Corner Name : dc_wcl
# RC Corner Name : cworst_m40c
# Analysis View : lt_cbest_func
# Delay Corner Name : dc_cblt
# RC Corner Name : cbest_m40c
# Analysis View : lt_cbest_scan
# Delay Corner Name : dc_cblt
# RC Corner Name : cbest_m40c
###############################################################
Nr. of Subtrees : 225
Nr. of Sinks : 9493
Nr. of Buffer : 975
Nr. of Level (including gates) : 25
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
No Driving Cell Specified!
Max trig. edge delay at sink(R): ****/dout_1d_reg_28_/CK 2924.6(ps)
Min trig. edge delay at sink(R): ****/availCnt_reg_6_/CK 2777.5(ps)