DDR2控制器，时序约束错误，哪位大神能帮帮忙？

JIANGXHUA · 发表于 2015-1-10 09:47:25

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时序约束时报如下错误，该怎么办？

PhysDesignRules:2449 - The computed value for the VCO operating frequency of PLL_ADV instance
my_mig_inst/memc3_infrastructure_inst/u_pll_adv is calculated to be 119.999998 MHz. This falls below the operating
range of the PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust either the input
frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to
achieve a VCO frequency within the rated operating range for this device.

573436967 · 发表于 2015-12-15 10:53:44

请问你测试时候行为仿真怎么好用的。我的初始化信号怎么一直为0.

[求助] DDR2控制器，时序约束错误，哪位大神能帮帮忙？

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