Synopsys (HR) 热招 Verification Manager /DDR PHY CAE

Domiliu

If you have any interest in the position, please send your bilingual resume as attachments to
dmliu@synopsys.com

1\ Job title: Verification Manager

Location: Wuhan

As a CAE Manager for Emulation/Transactor development, based in Wuhan, candidate will be responsible for leading a team to deliver successful development of emulation transactors and deployment of Synopsys emulation solution(ZeBu) to a growing customer base in AsiaPacific. The CAE responsibilities include developing transactors covering different protocols, onsite deployment of industry leading emulation technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement. Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex emulation issues for customers cutting edge asic designs. The position offers a great opportunity to grow by learning state-of-art emulation flows from Synopsys.

Requirements:

-MS or PhD majored in EE with more than 5 years of IC design/verification/emulation experiences. -Good knowledge of high-level verification and emulation methodologies and strong communication skills are required.
-Ability to work with customers and R&D teams is important. Real project experience in ASIC/SoC emulation or FPGA development and good expertise on popular emulators like Palladium/Veloce/Zebu and Xilinx/Altera FPGA are required.
-Proficient with hdl (verilog/VHDL), HVL(systemverilog), C/C++, Unix. Experience on VMM/OVM/UVM and knowledge of VIP/AVIP and simulator-emulator co-emulation are preferred.

2\(Sr./ Staff )DDR PHY CAE

Location: Shanghai/Shenzhen

Description

As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP.

You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. You will be interfacing with our Design Engineering team to report on any issues related to the IP’s design, reliability and maintenance or defects.

You will have the capability to design and implement solutions to complex application problems independently with little guidance.

You will be authoring application-notes and/or white-papers that promote the IP’s ease of use, or address specific challenges in the IP’s usage.

You may be called upon to author technical papers and present them in peer-reviewed technical publications or conferences.

You will have regular contact with external customers and internal contacts across cross-functional teams. Occasional travel will be required.

Requirements

Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design.

Strong communication skills and ability to interact with customers as well as peers is required.

Recent experience with ASIC implementation EDA tools and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired.

Domain knowledge of the DDR3/2 Protocols with relevant experience is a plus.

Hardware debug and troubleshooting skills are highly desirable.

Relevant experience in design, implementation or technical support with mixed signal designs is highly desired.

Domiliu

Synopsys 极好的机会 持续招聘中！！