能否解释一下run_tc中,用VCS仿真时的vcs +acc +vpi -sverilog $UVM_HOME/src/dpi/uvm_dpi.cc的作用呢?我现在仿真过程中,用frontdoor对reg_model进行read/write都正常,backdoor在peek()时会报以下错误:
UVM_ERROR: get: unable to locate hdl path top.xx.xxx.fieldA. Either the name is incorrect, or you may not have PLI/ACC visibility to that name。
我在run的命令中没有加入cs +acc +vpi -sverilog $UVM_HOME/src/dpi/uvm_dpi.cc,加入这句话以后,编译完了会报multiple definition of "uvm_hdl_read"之类的错误。