conformal验证DC综合后的网表

似水如烟

如题。因为综合过程中会remove掉相关常值寄存器、悬空net等逻辑，如果用formality的话，可以读入综合过程中读入的svf文件来识别DC过程中的动作。但是如果采用conformal来做的话，如何处理，svf如何读入？

午后乐天派

有答案了吗？我也想知道

gay007

laurancy_gan

提问5， 6年了，也没人知道吗。。。。

weihemin

To record setup information for formal verification tools other than Formality, use the
set_vsdc command. The command records setup information in V-SDC format for efficient
compare point matching in third-party formal verification tools. The V-SDC format is a subset
of the automated setup file used by Formality. The V-SDC file is written in plain text, whereas
the automated setup file is encrypted and compressed.
The set_vsdc command records the following operations:
• Name changes resulting from operations such as ungroup, group, or uniquify, or the
automatic uniquify process in compile with combinations of group and ungroup. These
operation can change the names of design objects such as registers, black boxes, and
top-level ports
• Operations performed by the compile command that result in register optimizations.

weihemin

可以使用set_vsdc命令

@@@12

weihemin 发表于 2022-5-31 11:36
可以使用set_vsdc命令

是在DC的时候用set_vsdc命令生成了vsdc文件，再用read setup information命令读进去吗？但感觉我读进去了后结果好像变化不大

ustcwangl

@@@12 发表于 2022-8-9 18:45
是在DC的时候用set_vsdc命令生成了vsdc文件，再用read setup information命令读进去吗？但感觉我读进去了 ...

你也需要一些其他设置的，比如remodel或者set_flatten_model，map method